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NOCS 2016 : 10th International Symposium on Networks-on-Chip (NOCS 2016)

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Conference Series : Networks-on-Chips
 
Link: http://www.arc.ics.keio.ac.jp/nocs16/index.html
 
When Aug 31, 2016 - Sep 2, 2016
Where Nara, Japan
Abstract Registration Due Feb 5, 2016
Submission Deadline Feb 12, 2016
Notification Due Apr 8, 2016
Final Version Due May 18, 2016
Categories    networks on chip   architecture   high performance computing   system on chip
 

Call For Papers

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

NoC Architecture and Design
Network architecture (topology, routing, arbitration)
NoC Quality of Service
Timing, synchronous/asynchronous communication
Network interface issues
NoC design methodologies and tools
Mapping of applications onto NoCs
Signaling and circuit design for NoC links
NoC at the Un-Core and System-level
Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols, and NoCs
NoC support for memory and cache access
OS support for NoCs
Programming models including shared memory, message passing, and novel models
Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks
Novel NoC Technologies
New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc
NoCs for 3D and 2.5D packages
Package-specific NoC design
Optical, RF, and emerging technologies for on-chip/in-package interconnects
NoC Application
NoC case studies
Application-specific NoC designs
NoC designs for heterogeneous many-core systems, fused CPU-GPU architectures, FPGA-based systems, etc
NoC Analysis, Verification, and Modeling
Modeling, simulation, and synthesis of NoCs
Verification, debug, and test of NoCs
Metrics and benchmarks for NoCs
Scalable modeling of NoCs
NoC Optimization
For power/energy efficiency
For thermal efficiency and darksilicon
For dependable architectures
For communication efficient algorithms
Submission Rules

Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. The program committee in a double-blind review process will evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference or journal at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Please see the paper submission instructions for details.

Proposals for special sessions, panels, tutorials, and demos are also invited. Please see the paper submission instructions for special session, panel, tutorial, and demo proposals for details.

Important Dates

Abstract registration deadline February 5, 2016
Full paper submission deadline February 12, 2016
Notification of acceptance April 8, 2016
Final version due May 18, 2016

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