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SELSE 2013 : IEEE Workshop on Silicon Errors in Logic - System Effects


When Mar 26, 2013 - Mar 27, 2013
Where Stanford, California, USA
Submission Deadline Dec 14, 2012
Notification Due Feb 2, 2013
Final Version Due Mar 4, 2013
Categories    reliability   soft-errors   SEU   system effects

Call For Papers

The growing complexity and shrinking geometries of modern device technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching. Growing concern about intermittent errors, unstable storage cells, and the effects of aging are influencing system design. This workshop provides a forum for discussing current research and practice in system-level error management. Participants from industry and academia explore both current technologies and future research directions (including nanotechnology). We are soliciting papers that address the system-level effects of errors from a variety of perspectives: architectural, logical, circuit-level, and semiconductor processes. Case studies are also solicited.

Key areas of interest are (but not limited to):

Technology trends and the impact on error rates
New error mitigation techniques
Characterizing the overhead and design complexity of error mitigation techniques
Case studies describing the engineering tradeoffs necessary to decide what mitigation technique to apply
Experimental data
System-level models: derating factors and validation of error models
Error handling protocols (higher-level protocols for robust system design)

Authors are requested to submit extended abstracts for review before December 14, 2012. Extended abstracts will be considered for both oral and poster presentation. All accepted submissions are included in the workshop proceedings. Authors will be notified of paper outcome by February 2, 2013. Camera-ready papers are due on March 4, 2013.

Additional information and guidelines for submission are available at Submissions should be PDF or Microsoft Word files in IEEE format that do not exceed four printed pages. Camera-ready papers can be up to six pages in length in IEEE format. Papers are not made available through IEEE and authors retain the copyright of their work. Authors may optionally choose to make their final papers available online through the SELSE webpage.

Important dates:

Extended abstract submission: December 14, 2012
Authors notification: February 2, 2013
Camera-ready submission: March 4, 2013

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