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VPA 2014 : 1st Workshop on Visual Performance Analysis (VPA) | |||||||||||||||
Link: http://cedmav.org/vpa2014 | |||||||||||||||
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Call For Papers | |||||||||||||||
1st Workshop on Visual Performance Analysis (VPA)
Held in conjunction with SC14: The International Conference on High Performance Computing, Networking, Storage and Analysis New Orleans, LA, USA November 21, 2014 Extended Submission Deadline: August 8, 2014 Over the last decades an incredible amount of resources has been devoted to building ever more powerful supercomputers. However, exploiting the full capabilities of these machines is becoming exponentially more difficult with each new generation of hardware. To help understand and optimize the behavior of massively parallel simulations the performance analysis community has created a wide range of tools and APIs to collect performance data, such as flop counts, network traffic or cache behavior at the largest scale. However, this success has created a new challenge, as the resulting data is far too large and too complex to be analyzed in a straightforward manner. Therefore, new automatic analysis approaches must be developed to allow application developers to intuitively understand the multiple, interdependent effects that their algorithmic choices have on the final performance. This workshop will bring together researchers and practitioners from the areas of performance analysis, application optimization, visualization, and data analysis and provide a forum to discuss novel ideas on how to improve performance understanding, analysis and optimization through novel techniques in scientific and information visualization. Workshop Topics: - Scalable displays of performance data - Interactive visualization of performance data - Data models to enable data analysis and visualization - Graph representation of unstructured performance data - Collection and representation of meta data to enable fine grained attribution - Message trace visualization - Memory and network traffic visualization - Representation of hardware architectures Paper Submission: We solicit two types of papers both covering original and previously unpublished ideas: 8 page regular papers and 4 page position papers. To be considered, your manuscript should be formatted according to the double-column IEEE format for Conference Proceedings (IEEEtran LaTeX Class (template) V1.8 packages and IEEEtran V1.12 BibTeX (bibliography)). Margins and font sizes should not be modified. The templates for "IEEEtran LaTeX Class (template) V1.8 packages and IEEEtran V1.12 BibTeX (bibliography)" can be found at http://www.ieee.org/conferences_events/conferences/publishing/templates.html All papers must be submitted through Easychair at: https://www.easychair.org/conferences/?conf=vpa14 Important Dates - August 8th: extended submission deadline for papers - September 15th: notification of acceptance - October 6th: final paper and copyrights due Workshop Organizers - Peer-Timo Bremer, Lawrence Livermore National Laboratory - Bernd Mohr, Jülich Supercomputing Centre - Valerio Pascucci, University of Utah - Martin Schulz, Lawrence Livermore National Laboratory Contact - vpa14@easychair.org Program Committee - Carlos Scheidegger, AT&T - Naoya Maruyama, RIKEN AICS - Felix Wolf, German Research School for Simulation Sciences - Matthias Mueller, RWTH Aachen University - Holger Brunst, ZIH / TU Dresden - Joshua Levine, Clemson University - Derek Wang, Charlotte Visualization Center, UNCC - Todd Gamblin, Lawrence Livermore National Laboratory - Hank Childs, University of Oregon - Markus Geimer, Jülich Supercomputing Centre - Judit Gimenez, Barcelona Supercomputing Center / Universitat Politècnica de Catalunya - Remco Chang, Tufts University |
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