Complex silicon devices are increasingly controlling critical systems where safety and reliability are key concerns. Silicon technology is subject to numerous failure modes which can be broadly classified into soft- error effects (due to natural radiation) and life-time effects (e.g. electro-migration, NBTI, HCI). It is necessary to consider all of these failure modes and how they propagate through the system and produce user-visible effects. There are no consistent tools or methodologies to address this problem. Current ad-hoc approaches are not able to cope with the diversity of technology failure modes, increased design sizes and the complex relationships between consumers and suppliers of electronic components. RIIF (Reliability Information Interchange Format), is an initiative to develop a standard modelling language for specifying the failure mechanisms in silicon devices and systems built using these devices. One of the main goals of the workshop is to establish the requirements for the RIIF and assess the current implementation.
Submissions

The workshop is co-located with the DATE conference and will include talks from industry experts including IP suppliers, fabless partners, foundries and end-users from the automotive and other industries. We are soliciting short papers to be presented during a poster-session. Authors are invited to submit a 2-4 page abstract on topics relating to the modelling of failure mechanisms in silicon-devices (soft-errors, life-time effects), design and specification of reliable IP components and integrated circuits and safety, reliability analysis. Papers will be distributed on-line and through printed proceedings, but not through IEEE. You retain the copyright of your work.

Important Dates

Submission Deadline: January 18th 2013

Author Notification: February 22nd 2013

Final Paper Due: March 11th 2013