Scope: In IC designs today, analog content is no longer a small portion of silicon as it was in the past. With various interfaces such as PCIe, DDR, Display-IO, HT, and other components such as PLLs, DACs, Temperature Sensors, the proportion of silicon die area covered by analog circuits is continually increasing with each design generation. Starting with 65nm process technology, a growing market need for high speeds, large bandwidths and small geometries have made designs a lot more complex in terms of testability and manufacturability. Majority of test for analog portions of a chip have been marginalized to characterization on the ATE and boards. This characterization is often planned around various electrical and thermal corners and the outcome is heavily dependent on process technology. More often than not, rigorous testing of the full range of properties of an analog circuit is neglected during production-ramp and production. Prime among the many reasons for this lack of rigor in test of analog circuits is overall test cost.

In this workshop, we will bring to fore, various issues associated with test and validation of high speed analog circuits, including innovative solutions for high parametric coverage and lower test cost. The scope of the workshop includes:

Design-for-test, including BIST and loop-back test.

Design for characterization and validation, including on-die sensors and test structures

ATE technology for high speed analog measurements that address accuracy, bandwidth and efficiency.

Board technology for load-board and probe-card design to address ATE-based test and characterization.

Economics of test, test cost and yield optimization


Representative topics include, but are not limited to:

Analog IP Design considerations

Analog DfT methods

Parametric Defects and Process Variations

Embedded Test & Diagnostics

Characterization, Ramp, and Production testing of Analog components

Fault models, defect modeling

Yield analysis and recovery

Author information

To present at the Workshop, authors are invited to submit paper proposals. The proposals may be extended abstracts (200 words) or full papers. Each submission should include: title, full name and affiliation of all authors, a short abstract of 50 words, and keywords. Also, identify a contact author and include a complete correspondence address, phone number, fax number, and e-mail address.

Submit a copy of your paper proposal by Postscript, or PDF, via E-mail. Proposals for panel discussions are also invited. Submissions are due no later than October 4th, 2010.

Submit your paper proposal to:

Sassan Tabatabaei E-mail: stabatabaei@sitime.com

Authors will be notified of the disposition of their papers by October 10th, 2010.

Authors of accepted papers to submit an illustrated text by October 22nd, 2010 for inclusion in the Workshop Notes, which will be provided to the attendees.