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CASES 2018
Call for Papers
International Conference on
Compilers, Architectures, and Synthesis for Embedded Systems
September 30 – October 5, 2018, Torino, Italy
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CASES is a premier forum where researchers, developers and practitioners
exchange information on the latest advances in compilers and
architectures for high-performance, low-power embedded systems. The
conference has a long tradition of showcasing leading edge research in
embedded processor, memory, interconnect, storage architectures and
related compiler techniques targeting performance, power, security,
reliability, predictability issues for both traditional and emerging
application domains. We also invite innovative papers addressing design,
synthesis & optimization challenges in heterogeneous, accelerator-rich
architectures.


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Timeline
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Journal-Track Submissions
- Abstract: March 27, 2018
- Full Paper: April 3, 2018 (firm)

Work-in-Progress Submissions
- May 30, 2018 (firm)

Notification of Acceptance
- July 1, 2018 (both tracks)


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Topics of Interests / Tracks
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Compilers for Embedded Systems:
Compilation for power and performance; Compiler support for CPU, GPU,
reconfigurable computing, heterogeneous multi-core SoC; Compilation for
memory, storage, and on-chip communications.

Processor Architectures:
Embedded and mobile processor micro-architecture, Multi- and many-core
processors, GPU architectures, Reconfigurable computing including FPGAs
and CGRAs, Application-Specific processor design, 3D-stacked
architectures; Power- and energy-efficient architectures.

Memory and Storage:
Memory system architecture; Non-volatile and other emerging memory
technologies; Scratchpad memory, caches and compiler-controlled memories;
storage organization including flash storage.

On-chip communication and I/O:
Networks-on-chip architectures and design methodologies; on-chip
communication synthesis, analysis, and optimization; I/O management
in embedded systems.

Accelerators:
Synthesis, optimization, and Design-space exploration of high-
performance, low-power accelerators; Novel design paradigms for
accelerators including approximate computing.

Security, Reliability, and Predictability:
Secure architectures, hardware security, and compilation for software
security; Architecture and compiler techniques for reliability and aging;
Modeling, design, analysis, and optimization for timing and
predictability; Validation, verification, testing & debugging of embedded
software.

Emerging Applications:
Architectures and accelerators for machine learning, neuromorphic &
cognitive computing, data analytics; biologically inspired computing
systems.

Internet of Things (IoT) Day:
A special IoT Day will be jointly organized by the conferences in ESWEEK.
Articles aligned to the topics of interest for CASES, with distinct focus
on IoT platforms, wearables and other small form-factor devices are most
welcome.


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Paper Process
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CASES 2018 has a dual publication model with two tracks: Journal track
papers will be published in the IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems (TCAD) and Work-in-Progress
track papers will be published in the ESWEEK Proceedings. More details
at http://www.esweek.org/author-information


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Organization
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CASES Program Chairs:
Tulika Mitra, National University of Singapore, SG
Akash Kumar, Technical University of Dresden, DE

ESWEEK General Chairs:
Soonhoi Ha, Seoul National University, KR
Petru Eles, Linköping University, SE

www.esweek.org