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HiPEAC 2020 : 15th International Conference on High Performance Embedded Architectures and Compilers

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Conference Series : High Performance Embedded Architectures and Compilers
 
Link: https://www.hipeac.net/events/#/conference/
 
When Jan 20, 2020 - Jan 22, 2020
Where Bologna, Italy
Submission Deadline Jun 1, 2019
Categories    computer architecture   programming model   compiler   operating system
 

Call For Papers

The HiPEAC conference is the premier European forum for experts in computer architecture, programming models, compilers and operating systems for embedded and general-purpose systems.

The 15th HiPEAC conference will take place in Bologna, Italy from Monday 20 January to Wednesday 22 January, 2020. Associated workshops, tutorials, special sessions, several large poster sessions and an industrial exhibition will run in parallel with the conference. The three-day event attracts over 500 delegates each year.

Topics of interest include, but are not limited to:
• Processor, memory, interconnect, and storage architectures
• Parallel, multi-core and heterogeneous systems
• Interconnection networks
• Architectural support for programming productivity
• Power, performance and implementation efficient designs
• Reliability and real-time support in processors, compilers and run-time systems
• Application-specific processors, accelerators and reconfigurable processors
• Architecture and programming environments for GPU-based computing
• Architectural simulation and methodology
• Architectural and run-time support for programming languages
• Programming models, frameworks and environments for exploiting parallelism
• Compiler techniques
• Feedback-directed optimization
• Program characterization and analysis techniques
• Dynamic compilation, adaptive execution, and continuous profiling/optimization
• Binary translation/optimization
• Code size/memory footprint optimizations
• Architectures for emerging technologies such as neuromorphic, photonics, quantum, etc.

Journal-first publication model
HiPEAC has been pioneering the journal-first publication model. Journal-first means that the manuscript selection process for the conference is outsourced to a journal (ACM TACO). Manuscripts can be submitted to the journal at any time throughout the year as regular journal submissions. For all manuscripts submitted before June 1, ACM TACO guarantees that the final decision (including two rounds of revision) will be communicated before November 15. All authors of original work papers accepted in the journal between November 15, 2018 and November 15, 2019 will get an invitation to present their work during the paper track of the HiPEAC conference. There are no conference proceedings published.

ACM TACO = Open access
ACM TACO will be an open access journal from July 1, 2018 to July 1, 2022. Hence, all past and future ACM TACO papers, including all papers accepted to this call, will be open access to all until July 2022 (at no cost to the authors).

Submission deadline
Manuscripts can be submitted continuously. Manuscripts submitted before June 1, 2019 will get an invitation for HiPEAC 2020, if accepted. Manuscripts submitted after June 1, 2019 will be invited for HiPEAC 2021, if accepted.

Related Resources

CASES 2021   International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
OpenSuCo @ ISC HPC 2017   2017 International Workshop on Open Source Supercomputing
CF 2021   ACM International Conference on Computing Frontiers 2021
IJCSA 2021   International Journal on Computational Science & Applications
ALCHEMY 2021   Architecture, Languages, Compilation and Hardware support for EMerging and Heterogeneous sYstems
CHEOPS 2021   Workshop on Challenges and Opportunities of Efficient and Performant Storage Systems
ISC HPC 2021   ISC HIGH PERFORMANCE 2021 DIGITAL
COOL Chips 24   IEEE Symposium on Low-Power and High-Speed Chips and Systems
HPDC 2021   High Performance Distributed Computing
PARMA-DITAM 2021   PARMA-DITAM: 12th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures & 10th Workshop on Design Tools and Architectures for Multi-Core