It is widely recognized that process variation is emerging as a fundamental challenge to IC design in scaled CMOS technology; and it will have profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled with improvements in the manufacturing process, the industry is starting to accept the fact that some of the effects are better mitigated during the design process. Handling variability in the design process will require accurate and appropriate models of variability and its dependence on designable parameters (i.e. layout), and its spatial and temporal distributions. It also requires carefully designed test structures and proper statistical data analysis methods to extract meaningful models from large volumes of silicon measurements. The resulting compact modeling of systematic, random, spatial, and temporal variations is essential to abstract the physical level variations into a format the designers (and more importantly, the tools they use) can utilize. This workshop provides a forum to discuss current practice as well as near future research needs in test structure design, variability characterization, compact variability modeling, and statistical simulation.

Key Topics

Physics mechanisms and technology trends of device-level variations

First-principles simulation methods for predicting variability

Time-dependent variation and their interaction with other variation sources

Compact modeling of variations in devices and interconnect

Device and circuit level modeling techniques

Test structure design for variability

Variability characterization, bounding and extraction

Statistical data analysis and model extraction methods

Novel implementation and simulation techniques for dealing with variability

Tentative Program

Session I: Atomistic level variations

Tsu-Jae King Liu (Univ. of California, Berkeley): Impact of atomistic variability on device performance

Scott Roy (Univ. of Glasgow): Atomistic simulation of variability

Naoki Tega (Hitachi): Randome telegraph noise

Session II: Process induced variations

Paul Newman (Intel): Process variations in scaled IC design

Puneet Gupta (Univ. Of Californa, Los Angeles): Advanced lithography effects

Victor Moroz (Synopsys): Strain effect

Session III: Morning Poster Session

Session IV: Emerging parametric variations and extraction

Tanya Nigam (Global Foundries): Aging effect in scaled CMOS

Abe Elfadel (IBM): Interconnect variability and extraction

Xin Li (Cargegie Mellon Univ.): Virtual probe: minimum-cost silicon characterization of nanoscale IC

Session V: Characterization of device and circuit variability

Vikas Chandra (ARM): Variations in standard cell library

Lawrence Clark (Arizona State Univ.): In-situ characterization of SRAM variability

Chris Kim (Univ. of Minnesota): Temporal effect in scaled CMOS circuits

Session VI: Afternoon Poster Session

Workshop Organizers

Technical Advisor: Sani Nassif, IBM Austin Research Lab, nassif AT us DOT ibm DOT com

Frank Liu, IBM Austin Research Lab, frankliu AT us DOT ibm DOT com

Yu (Kevin) Cao, Arizona State University, ycao AT asu DOT edu

Hidetoshi Onodera, Kyoto University, onodera AT vlsi DOT kuee DOT kyoto-u DOT ac DOT jp

Dennis Sylvester, University of Michigan, dennis AT eecs DOT umich DOT edu