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FPGA 2010 : ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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Conference Series : Field Programmable Gate Arrays
 
Link: http://www.isfpga.org/
 
When Feb 21, 2010 - Feb 23, 2010
Where Monterey, CA, USA
Submission Deadline Sep 20, 2009
Notification Due Nov 13, 2009
Final Version Due Dec 6, 2009
Categories    design automation
 

Call For Papers

Eighteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

Monterey Beach Hotel
Monterey, California
February 21-23, 2010

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for presentation of advances in all areas related to FPGA technology. For FPGA 2010, we are soliciting original submissions describing novel research and developments in the following (and related) areas of interest:

* FPGA Architecture: Novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.), design of routing fabric, I/O interfaces, new commercial architectures and architectural features.
* FPGA Circuit Design: Novel FPGA circuits and circuit-level techniques, impact of process and design technologies, methods for analyzing and improving issues with soft-errors, leakage, static and dynamic power, clocking, power grid, yield, manufacturability, reliability, test; studies on future device technologies (e.g. nano-scale, 3D gate) for FPGAs.
* CAD for FPGAs: Placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification, CAD for FPGA-based accelerators, CAD for incremental FPGA design and on-line design mapping and optimization, CAD for modeling, analysis and optimization of timing and power.
* High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific models, languages, tools, and techniques to facilitate the design, development, debugging, verification, and deployment of large-scale and high-performance FPGA-based applications and systems – e.g. DSP, networking or embedded system tools and methodologies.
* FPGA-Based and FPGA-like computing engines: Compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software, rapid-prototyping.
* Design Studies: Innovative uses of FPGA fabric for computation, exploitation of FPGA features and architectures, optimization of FPGA-based cores (e.g. arithmetic, DSP, security, embedded processors, memory interfaces, or other functions).
* Applications: Implementation of designs on FPGAs to achieve high-performance, low-power, or high-reliability. Novel design algorithms which take advantage of FPGA features. Application-domain studies to analyze or improve FPGA implementation for networking, DSP, embedded, audio/video, automotive, imaging and other relevant areas.
* Panel Outlines: Topic proposals for the traditional Monday night Panel Session at FPGA.

Authors are invited to submit English language PDF of their paper or panel proposal by September 20, 2009. Submitted papers will be considered for acceptance as a full paper (10 pages maximum), as a short paper (4 pages), or as a poster.

FPGA is moving this year to a blind reviewing system. Manuscripts must not identify authors or their affiliations. Self-references should be shown as "Removed for blind review". Papers that identify authors will not be considered. Submission instructions and further information will be available at the conference website: http://www.isfpga.org.

All papers should use the ACM formatting templates available at: http://www.acm.org/sigs/pubs/proceed/template.html.

Notification of acceptance will be sent by November 13, 2009. The authors of accepted papers will be required to submit the final camera-ready copy by December 6, 2009. A proceedings of the accepted papers will be published by ACM and included in the Annual ACM/SIGDA CD-ROM Compendium publication.

Selected papers published at FPGA will be invited to submit an extended version to a special issue of ACM Transactions on Reconfigurable Technology and Systems.
Address questions to: John Wawrzynek, Program Chair FPGA 2010
Department of EECS
University of California
Berkeley, CA 94720
Phone : (510) 643-9434
Email : johnw [at] eecs [dot] berkeley [dot] edu

Organizing Committee
General Chair: Peter Cheung, Imperial College
Program Chair: John Wawrzynek, University of California, Berkeley
Finance Chair: Paul Chow, University of Toronto
Publicity Chair: Katherine Compton, University of Wisconsin-Madison

Key Dates
Submission Deadline: September 20, 2009
Acceptance Notification: November 13, 2009
Camera-Ready Copy: December 6, 2009
Conference Dates: February 21-23, 2010

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