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PACT 2017 : International Conference on Parallel Architectures and Compilation Techniques


Conference Series : International Conference on Parallel Architectures and Compilation Techniques
When Sep 13, 2017 - Sep 17, 2017
Where Portland, Oregon, USA
Submission Deadline Mar 14, 2017
Notification Due May 24, 2017
Final Version Due Jul 19, 2017
Categories    computer architecture   compilers   parallel computing

Call For Papers

Call for Participation – 26th International Conference on Parallel Architectures and Compilation Techniques (PACT 2017)
Sept 9-13th, 2017
Portland, Oregon

The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest. We invite attendees to register for our exciting program this year consisting of many informative workshops/tutorials, leading industry keynotes and conference papers and posters.

Important Dates:
- August 14th, 2017: Early Registration Deadline
- Sept 9-13th, 2017: Conference

PACT 2017 Preliminary Program

Workshop/Tutorial Schedule

Saturday, Sept 9th
Time ----------- Workshop/Tutorial Name
AM ------------- AVX-512: AVX-512 Architecture Insights, Compiler Optimizations and Code Modernization
AM ------------- AMD’s Radeon Open Compute and Heterogeneous System Architecture, an open standard foundation for deep learning and highly scalable compute
AM+PM -------- ANDARE: Workshop on Autotuning and Adaptivity Approaches for Energy Efficient HPC
AM+PM -------- Parallelism in Computer Arithmetic: From Circuits to GPU-Based Supercomputers
PM ------------- rCUDA: Boosting the performance of hybrid CPU-GPU clusters with rCUDA
PM ------------- Min-Move 2017: Hardware/Software Techniques for Minimizing Data Movement

Sunday, Sept 10th
Time ----------- Workshop/Tutorial Name
AM ------------- CISC 2017: Computational Intelligence & Soft Computing
AM+PM -------- AIM: Workshop on Architectures for Intelligent Machines
AM+PM -------- HARP: Intel Hardware Accelerator Research Program – A Tutorial for learning and using the Intel Xeon with integrated FPGA
AM+PM -------- OmpSs: Heterogeneous Parallel Programming with OmpSs
PM ------------- DFM 2017: Data Flow Models for Extreme-Scale Computing


Day 1 -- Monday, Sept 11th

7:00-8:00 Registration & Breakfast
8:00-8:30 Opening
8:30-9:30 Keynote: Marc Tremblay, Microsoft: “Cloud Performance – AI and Others”
9:30-10:00 Break

10:00-11:40 SESSION 1: Algorithms and data structures

• RCU-HTM: Combining RCU with HTM to Implement Highly Efficient Concurrent Binary Search Trees. Dimitrios Siakavaras, Konstantinos Nikas, Georgios Goumas, and Nectarios Koziris (National Technical University of Athens)
• Redesigning Go's Built-In Map to Support Concurrent Operations. Louis Jenkins (Bloomsburg University), Tingzhe Zhou (Lehigh University), and Michael Spear (Lehigh University)
• MultiGraph: Efficient Graph Processing on GPUs. Changwan Hong, Aravind Sukumaran-Rajam, Jinsung Kim, P. Sadayappan (The Ohio State University)
• An Ultra Low-power Hardware Accelerator for Acoustic Scoring in Speech Recognition Hamid Tabani, Jose Maria Arnau, Jordi Tubella, and Antonio Gonzalez (Universitat Politècnica de Catalunya)

11:40-1:10 Lunch

1:10-2:50 SESSION 2: Approximate and speculative computations

• DrMP: Mixed Precision-aware DRAM for High Performance Approximate and Precise Computing. Xianwei Zhang, Youtao Zhang, Bruce R. Childers, and Jun Yang (University of Pittsburgh)
• SAM: Optimizing Multithreaded Cores for Speculative Parallelism. Maleen Abeydeera, Suvinay Subramanian, Mark C. Jeffrey (MIT), Joel Emer (MIT/Nvidia), and Daniel Sanchez (MIT)
• Performance Improvement via Always-Abort HTM. Joseph Izraelevitz (University of Rochester), Lingxiang Xiang (Intel Corporation), and Michael L. Scott (University of Rochester)
• DRUT: An Efficient Turbo Boost Solution via Load Balancing in Decoupled Look-ahead Architecture. Raj Parihar (Cadence Design Systems), and Michael C. Huang (University of Rochester)

2:50-3:20 Break

3:20-4:10 SESSION 3: Data & Emerging Use Cases

• Proxy Benchmarks for Emerging Big-data Workloads. Reena Panda, and Lizy Kurian John (University of Texas at Austin)
• Lightweight Provenance Service for High Performance Computing. Dong Dai, Yong Chen (Texas Tech University), Philip Carns, John Jenkins, and Robert Ross (Argonne National Laboratory)



Day 2 – Sept 12th, Tuesday

7:30-8:30 Registration & Breakfast
8:30-9:30 Keynote – P. Sadayappan, Ohio State University
9:30-10:00 Break

10:00-11:40 SESSION 4: Memory 1

• Nexus: A New Approach to Replication in Distributed Shared Caches. Po-An Tsai (MIT), Nathan Beckmann (CMU), and Daniel Sanchez (MIT)
• Leeway: Highly Adaptive Cache Management. Priyank Faldu, and Boris Grot (University of Edinburgh)
• Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology. Vicent Selfa, Julio Sahuquillo (Universitat Politècnica de València), Lieven Eeckhout (UGENT), Salvador Petit, and Maria E. Gómez (Universitat Politècnica de València)
• Transparent Dual Memory Compression Architecture. Seikwon Kim, Seonyoung Lee, Taehoon Kim, and Jaehyuk Huh (KAIST)

11:40-1:10 Lunch

1:10-2:50 SESSION 5: Best Papers (GPU computing and energy efficiency)

• End-to-end Deep Learning of Optimization Heuristics. Chris Cummins, Pavlos Petoumenos (University of Edinburgh), Zheng Wang (Lancaster University), and Hugh Leather (University of Edinburgh)
• Graphie: Large-Scale Asynchronous Graph Traversals on Just a GPU. Wei Han, Daniel Edward Mawhirter (Colorado School of Mines), and Matthew Buland (Salesforce)
• A GPU-Friendly Skiplist Algorithm. Nurit Moscovici (Technion), Nachshon Cohen (EPFL), and Erez Petrank (Technion)
• A Formal Approach to Minimize Voltage Guardbands under Variation in Networks-on-Chip for Energy Efficiency. Raghavendra Pradyumna Pothukuchi (University of Illinois at Urbana Champaign), Amin Ansari (Qualcomm), Bhargava Gopi Reddy, and Josep Torrellas (University of Illinois at Urbana Champaign)

2:50-3:20 Break

3:20-5:00 SESSION 6: Memory 2

• Avoiding TLB Shootdowns through Self-invalidating TLB Entries. Amro Awad (Sandia National Laboratories), Arkaprava Basu (AMD Research), Sergey Blagodurov (AMD Research), Yan Solihin (North Carolina State University), and Gabriel H. Loh (AMD Research)
• Weak Memory Models: Balancing Definitional Simplicity and Implementation Flexibility. Sizhuo Zhang (MIT), Muralidaran Vijayaraghavan (MIT), and Arvind (MIT)
• Near-Memory Address Translation. Javier Picorel (EPFL), Djordje Jevdjic (University of Washington), and Babak Falsafi (EPFL)
• Restore-Free In-Place Checkpointing in Non-Volatile Main Memory for Scientific Algorithms. Mohammad Alshboul, Hussein Elnawawy, James Tuck, and Yan Solihin (North Carolina State University)

5:35pm Bus departs from hotel to excursion (cruise)

Day 3 – Sept 13th, Wednesday

7:30-8:30 Breakfast & Registration
8:30-9:30 Keynote: Pradeep Dubey, Intel: “AI and The Virtuous Cycle of Compute”
9:30-10:00 Break

10:00-10:50 ACM SRC Presentations
10:50-11:05 Break

11:05-12:20 SESSION 7: Translation

• SuperGraph-SLP Auto-Vectorization. Vasileios Porpodas (Intel Corporation)
• Exploiting Asymmetric SIMD Register Configurations in Cross-ISA Dynamic Binary Translation. Yu-Ping Liu (National Taiwan University), Ding-Yong Hong, Jan-Jan Wu (Academia Sinica), Sheng-Yu Fu, and Wei-Chung Hsu (National Taiwan University)
• A Generalized Framework for Automatic Scripting Language Parallelization. Taewook Oh, Stephen R. Beard, Nick P. Johnson, Sergiy Popovych, and David I. August (Princeton University)


Conference Close


The student travel grant application deadline for PACT-2017 is August 14th, 2017. Please send the application by email to the Student Travel Grant Chair, Carole-Jean Wu. Use the subject line "PACT 2017 Student Travel Grant Application for [Your-Last-Name, Your-First-Name]"

The travel grant application must include:

• The name of the student, the student's institution and advisor; US citizenship or residency information; membership in an under-represented group if applicable
• A resume (including IEEE and/or ACM student membership numbers if available)
• A cover letter stating the reason for attending PACT and a description of research interests
• A statement from the student's advisor confirming that you are a full-time student pursuing an MS/PhD or undergraduate research in the areas covered by PACT with the email titled "Student Travel Status Confirmation for [Your-Last-Name, Your-First-Name]". The confirmation email must be received prior to the application deadline
• Information about other sources of funding
• Estimate of conference-related expenses

For additional detail, please refer to



26th International Conference on Parallel Architectures & Compilation Techniques

September 9-13, 2017 Portland, Oregon, USA


The purpose of PACT 2017 is to bring together researchers from architecture, compilers, applications and languages to present and discuss innovative research of common interest.

PACT started as a Data Flow Workshop in conjunction with ISCA 1989 but quickly evolved into a unique venue at the intersection of classical parallel architecture and compilers.

Recently, PACT widened its scope to include insights useful for the design of machines and compilers from applications such as, but not limited to, machine learning, data analytics and computational biology.

PACT solicits novel papers, workshops, tutorials, and entries to an ACM student research competition on a broad range of topics that include, but are not limited to:

o Parallel architectures and computational models
o Compilers and tools for parallel computer systems
o Multicore, multithreaded, superscalar, and VLIW architectures
o Compiler/hardware support for hiding memory latencies
o Support for correctness in hardware and software
o Reconfigurable parallel computing
o Dynamic translation and optimization
o I/O issues in parallel computing and their relation to applications
o Parallel programming languages, algorithms and applications
o Middleware and run time system support for parallel computing
o Application-specific parallel systems
o Applications and experimental systems studies of parallel processing
o Relevant aspects of distributed computing and mobile computing
o Heterogeneous systems using various types of accelerators
o Insights from modern parallel applications such as, but not limited to,
machine learning, data analytics, and computational biology for the design
of parallel architectures and compilers


Paper Deadline....................March 14, 2017
Author Response Period........May 3-6, 2017
Author Notification...............May 24, 2017
Camera Ready Final Papers...July 19, 2017


Submitted papers will be evaluated on technical merits and clarity of presentation. Papers must contain sufficient information and be organized in such a way that their technical contribution and significance can be understood by a wide audience of computer scientists.

Submitted papers must be original material that has not been previously published in another conference or journal, nor is currently under review by another conference or journal. Papers are to be submitted for double-blind review. This means that author names as well as hints of identity are to be removed from the submitted paper.

Authors of accepted papers will be invited to formally submit their supporting materials to the Artifact Evaluation Committee. The task of this committee is to assess how the artifacts support the work described in the papers. Submission is volunta ry. Papers that go through the artifact evaluation process successfully will receive a seal of approval which will be printed on the first page of the papers in the proceedings.


General Chair: Ravi Iyer, Intel
Program Chair: David Padua, University of Illinois


ACM, IEEE Computer Society

AUTHORS TAKE NOTE: The official publication date is the date the proceedings
are made available in the ACM Digital Library or IEEE Xplore. This date may
be up to two weeks prior to the first day of the conference. The official
publication date affects the deadline for any patent filings related to
published work. (For those rare conferences whose proceedings are published
in the ACM Digital Library or IEEE Xplore after the conference is over, the
official publication date remains the first day of the conference.)

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