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GLSVLSI 2016 : IEEE GLSVLSI

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Conference Series : Great Lakes Symposium on VLSI
 
Link: http://www.glsvlsi.org/
 
When May 18, 2016 - May 20, 2016
Where Boston, MA, USA
Submission Deadline Dec 11, 2015
Notification Due Feb 12, 2016
Final Version Due Mar 11, 2016
Categories    vlsi design
 

Call For Papers

IEEE GLSVLSI 2016: [CALL FOR PAPERS]

May 18-20, 2016, Boston, MA, USA
http://www.glsvlsi.org/

The 26th edition of GLSVLSI will be held in Boston, Massachusetts, USA. Original, unpublished papers describing research in the general areas of VLSI and hardware design are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be available through the ACM Digital Library. Please visit http://www.glsvlsi.org/ for more information.
In addition to the traditional topic areas of GLSVLSI listed below, papers are solicited for a special theme of “Hardware and System Design for Security and Privacy”. We anticipate a special issue of a journal on the same topic for which selected papers related to the special theme will be invited to submit extended versions for consideration.

Program Tracks:
VLSI Design: design of ASICs, microprocessors/micro-architectures, embedded processors, analog/digital/mixed-signal systems, NoC, interconnects, memories, and FPGAs. ¬VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits.
Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction), algorithms and complexity analysis.
Low-Power and Power-Aware Design: circuits, microarchitectural techniques, temperature estimation/optimization, power estimation methodologies, and CAD tools.
Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault recoverability, and variation-aware design.
Emerging Technologies & Post-CMOS VLSI: nanotechnology, molecular electronics, quantum devices, biologically-inspired computing, spintronic technology, CNT, SET, RTD, QCA, VLSI aspects of sensor and sensor networks, etc. Emphasis should be on the analysis, novel circuits and architectures, modeling, CAD tools, and design methodologies for emerging technologies.

Abstract submission deadline: December 11, 2015
Extended Paper submission deadline: December 21, 2015
Acceptance Notification: February 12, 2016
Camera-Ready Paper Due: March 11, 2016

General Chairs
Ayse K. Coskun, Boston University, USA
Martin Margala, Univ. of Massachusetts Lowell, USA

Program Chairs
Laleh Behjat, University of Calgary, Canada
Jie Han, University of Alberta, Canada

Finance Chair
Sherief Reda, Brown University, USA

Special Sessions Chair
Ajay Joshi, Boston University, USA

Web Chair
Theocharis Theocharides, University of Cyprus, Cyprus

Proceedings Chair
Miroslav Velev, Aries Design Automation, USA

Registration Chair
Emre Salman, Stony Brook University, USA

Publicity Chairs
Aida Todri-Sanial, CNRS, LIRMM, France
Brett Meyer, McGill University, Canada

Steering Committee
David Atienza
José Ayala
Iris Bahar
Sanjukta Bhanja
Erik Brunvand
Yehea Ismail
Alex Jones
Hai (Helen) Li
Fabrizio Lombardi
Enrico Macii
Gang Qu
Ken Stevens
Yuan Xie
Zhiyuan Yan
Hai Zhou

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