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ETS 2016 : 21st IEEE European Test Symposium

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Conference Series : European Test Symposium
 
Link: http://www.ets16.nl/
 
When May 23, 2016 - May 27, 2016
Where Amsterdam, The Netherlands
Abstract Registration Due Dec 7, 2015
Submission Deadline Dec 14, 2015
Notification Due Feb 12, 2016
Final Version Due Mar 13, 2016
Categories    test   reliability   VLSI   verification
 

Call For Papers

The IEEE European Test Symposium (ETS) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, applications, hot topics and new trends in the area of electronic-based circuit and system testing. In 2016, ETS will take place in Amsterdam, The Netherlands. It is organized by the Delft University of Technology, which cosponsors the event jointly with the IEEE Council on Electronic Design Automation (CEDA).
ETS also features a special track on Emerging Test Strategies (ETS2), where new problems and ideas can be discussed in an informal atmosphere. ETS is the major event of the European Test Week that includes TSS (Test Spring School) and fringe workshops.

You are invited to participate and submit your contributions to ETS’16. The areas of interest include (but are not limited to) the following topics:
• Analog Test
• ATE Hardware and Software
• Automatic Test Generation
• Board Test and Diagnosis
• Boundary Scan Test
• Built-In Self-Test (BIST)
• Current-Based Test
• Defect-Based Test
• Delay and Performance Test
• Dependability and Functional Safety
• Design for Test (DfT)
• Design for Manufacturing (DfM)
• Diagnosis and Silicon Debug
• Economics of Test
• Emerging Technologies
• Failure Analysis
• Fault Modeling and Simulation
• Fault Tolerance
• GPU Test
• High-Speed I/O Test
• Low-Power IC Test
• Memory Test and Repair
• MEMS Test
• Microprocessor Test
• Mixed-Signal Test
• Multi-/Many-core Processor Test
• Nanotechnology Test
• On-line Test
• Power Issues in Test
• Reconfigurable System Test
• Reliability
• RF Test
• Security and Trust Issues in Test
• Self-Repair
• Sensor Test
• Signal Integrity Test
• SiP, Stacked, 3D IC Test
• SoC Test
• Soft Errors
• Standards in Test
• System Test
• Test Compression
• Test Quality
• Test Synthesis
• Thermal Issues in Test
• Validation and Verification
• Variability Issues in Test
• Yield Analysis and Enhancement

Publication – ETS'16 will produce electronic formal proceedings - with ISBN number, and to be indexed in the IEEE Xplore digital library and other bibliographical search engines.

Submissions – ETS’16 seeks original, unpublished contributions of the following types:
• Scientific papers for the Formal Proceedings, presenting novel and complete research work
• Contributions for the special track on Emerging Test Strategies (ETS2)

ETS’16 also seeks proposals for:
• Panels, embedded tutorials, and other special sessions
• Vendor presentations focusing on new features of test related products
• Fringe workshops, to be held on May 26 and 27
• Fringe meetings, to be held during the European Test Week

Further Information:

Said Hamdioui – General Chair
Delft University of Technology
The Netherlands
E-Mail: S.Hamdioui@tudelft.nl

Giorgio Di Natale – Program Chair
LIRMM – CNRS/University of Montpellier
France
E-Mail: giorgio.dinatale@lirmm.fr

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