Embedded system designs have evolved over time from single memory based designs to homogeneous processing units connected by an on-chip network. The number of cores to be integrated in a single chip is expected to rapidly increase in the coming years, moving from multi-core to many-core architectures and hold the promise of increasing performance through parallelism. As the number of cores integrated into a chip increases, the on-chip communication might becomes power and performance bottleneck. Given that Many-core Embedded Systems (MES) provide an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures, developing applications using the full power of NoC-based MES requires software developers to transition from writing serial programs to writing parallel programs. On top of that, managing many-core resources and designing scalable and faultless operating systems will be a tremendous challenge in future MES.

This special issue aims to foster the dissemination of high quality research in any new idea, method, theory and technique related to Many-core Embedded Systems design with a focus on parallel programming and architectures support issues, as well as to enhance its state-of-the-art. Original and research articles are solicited in all aspects of theoretical studies, programming methodologies, and experimental prototypes, modeling, scalable and fault tolerant design approaches and frameworks, algorithms, software and tools, analysis and comparison, and emerging implementations. The papers will be peer reviewed and selected on the basis of both their quality and their relevance to the theme of this special issue.

Topics of interest include:

Programming models and languages for EMS
Compilers and virtualization techniques
Many-core architecture customization
Memory management
Design space exploration for EMS
Runtime resource management
Thermal aware design
Fault-tolerant and reliable design
Specification and Formal modeling of EMS
Architectures, integration and synthesis for EMS
Heterogeneous multi-core and many-core architectures
Hardware/software co-design
Simulation, validation and verification
Test and fault tolerance
QoS management and performance analysis
Industrial practices and case studies
Operating systems and middleware
Scheduling and execution time analysis
Communication protocols and fault tolerance

Submission & Review Instruction

Submitted articles must not have been previously published or currently submitted for journal publication elsewhere. Submissions must be directly sent via the journal submission web site http://ees.elsevier.com/compeleceng/default.asp?pg=login.asp

The code for this special issue is SI-mces. Author must choose this Article Type at the time of submissions.

Each submitted paper will be reviewed by at least three reviewers. Criteria for evaluation:

Significance to the journal's audience and relevance to this special issue
Quality of the paper including originality, technical depth, significance of results, adequacy of priori works referenced, overall organization, clarity and readability, satisfactory English writing, sufficient support for assertions and conclusion, appropriate title, abstract adequately summarizes the paper, introduction provides proper orientation, clear tables and figures.



Schedule

Paper submission deadline: December 30, 2015
Notification of the first review: March 25, 2015
Revised paper submission: April 31, 2016
Notification of the re-review: May 28, 2016
Minor revision deadline: June 15, 2016
Final notification: July 30, 2016
Final manuscript: August 15, 2016
Publication: Nov. 2016

Guest Editors

Prof. Robert C.-H. Hsu
Chung Hua University, Taiwan
chh@chu.edu.tw
http://people.chu.edu.tw/~chh/

Prof. Victor Malyskin
Russian Academy of Sciences, Russian Federation
malysh@ssd.sscc.ru
http://ssd.sscc.ru/en/users/malyshkin

Prof. Xiaoming Li
University of Delaware, USA
xli@udel.edu
http://www.eecis.udel.edu/~xli/