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SDAF 2015 : Simulation in the Design Automation Flow

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Link: http://duniptech.com/conference/summersim15/CFP/CFP_SEDAF15.pdf
 
When Jul 26, 2015 - Jul 29, 2015
Where Chicago
Submission Deadline Mar 20, 2015
Notification Due Mar 31, 2015
Final Version Due Apr 12, 2015
Categories    design automation   simulation   high-level synthesis   hw acceleration
 

Call For Papers

This track is specially intended to those works tackling the simulation problem during the entire design flow for electrical circuits. In the last few years, simulations have become an important mechanism to detect errors in the earlier design stages, allowing the designers to correct them and accelerate the time to market of their circuits. Most commercial and academic EDA tools make use of simulations to help designers find flaws and debug the incorrect behavior of the target hardware.
Simulations during the design stage can be mainly classified into three categories: behavioral, structural and post-route, each of them with a different accuracy/runtime tradeoff. It is a major challenge to optimize this relationship either with new models or utilizing hardware platforms to increase the simulation speed without losing or sacrificing very little precision.
Simulation methods also depends on the selected architecture. Thus, the centralized or distributed nature of the datapath controller determines the model and how to simulate it. Works dealing with unconventional non-centralized architectures are especially encouraged in this track. Another important factor is the presence of dynamic events, such as delay variations or variable latency blocks. Hence, the introduction of external sources of variability or the module libraries, on which the designs are based, are also critical. Conventional simulators use to be static, so simulation engines able to handle with these unexpected events are also encouraged.
Many of the topic areas involve a deep knowledge about simulation, Design Automation, High-Level Synthesis and in general computer architecture. Modeling, distributed simulations or GPU and FPGA simulating platforms are among the hot-topics of ACM-SIGSIM, and have been heavily promoted at WSC’14 or ACM-SIGSIM PADS.

High-quality papers in all aspects of simulation during the Design Automation flow are solicited, including (but not restricted to) the following areas:
- Advanced modeling techniques in High-Level Syntehsis, and their execution using novel simulation algorithms.
- Parallel algorithms and high performance simulation during the synthesis, placement and routing stages.
- GPU, FPGA and hybrid architecture acceleration.
- Simulation based on distributed controllers.
- Process and delay variation modeling and simulation in datapaths.
- Radiation effects simulation in reliable circuits.
- Datapaths based on variable latency blocks simulation.
- Power and energy simulations to evaluate the design automation algorithms.
- Temperature and aging simulations during the design flow.
- MPSoCs and 3D chips simulation during the synthesis, placement and routing stages.
- Simulation during the Design Space Exploration.
- Simulation visualization techniques to help debug designers.

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