IDEA 2015 : Investigating Dataflow in Embedded computing Architecture
Call For Papers
===== Call for Extended Abstracts - IDEA 2015 =====
1st International Workshop on Investigating Dataflow in Embedded computing Architecture
In conjunction with with HiPEAC 2015
===== Important Dates =====
Abstract Submission Deadline: October 20, 2014 (Extended)
Notification of Acceptance: 15 November 2014
Camera-Ready Version Submission Deadline: 6 December 2014
Workshop date: 21 January 2015.
HiPEAC Conference Date: 18 – 21 January 2015
===== General Scope =====
The dataflow model of computation offers a powerful perspective on parallel computations that may be conditioned in terms of data dependencies. It dates back to the sixties and has applications in the design of real-time stream-processing systems, especially in the area of digital signal processing. As a model of computation that fits embedded multi-core system architectures, dataflow is gaining renewed popularity, with an influx of work ranging from using dataflow as a programming paradigm, for performance analysis, or for design optimization.
Dataflow is gaining popularity among researchers around Europe and the world. However, research on dataflow is limited to small pockets in different communities without a common forum for discussion. The goal of this workshop is to provide a platform dedicated to the discussion of emerging ideas in modeling and analysis of present and future high performance computing architectures using dataflow. Furthermore we hope to increase exposure and strengthen communication among different research groups working on dataflow.
We especially invite new PhD students and Post-Docs exploring into dataflow modeling and analysis. The workshop offers an informal setting to discuss and exchange ideas, and to get in touch with experts in the field. Topics of interest include, but are not limited to:
• Dataflow as a programming paradigm for embedded applications.
• Real-time scheduling, analysis, response modeling techniques, for embedded systems.
• Tools for compilation, evaluation, optimization or synthesis of applications for heterogeneous / homogeneous multi-processor systems with respect to shared bus, shared memory, buffer sizing, power consumption, etc.
• New variants of the dataflow model of computation to capture dynamic execution behavior.
• Analysis of data flow graphs using other models of computation.
===== Organizing Committee =====
Waheed Ahmad (University of Twente, Twente)
Robert de Groote (University of Twente, Twente)
Alok Lele (University of Eindhoven, Eindhoven)
===== Technical Program Committee =====
Benny Åkesson (Czech Technical University, Prague)
Marco Bekooij (NXP Research, Eindhoven)
Shuvra S. Bhattacharyya (University of Maryland, College Park)
Pieter J. L. Cuijpers (University of Eindhoven, Eindhoven)
Michael Glaß, (Friedrich-Alexander-Universität, Erlangen-Nürnberg)
Kim Grüttner (OFFIS, Oldenburg)
Alix Munier Kordon (INRIA / LIP6, Paris)
Orlando Moreira (Ericsson, Eindhoven)
Luis Miguel Pinho (CISTER, Porto)
Petro Poplavko (VERIMAG, Grenoble)
Gerard Smit (University of Twente, Twente)
Sander Stuijk (University of Eindhoven, Eindhoven)
Jean-Pierre Talpin (INRIA, Rennes)
Xue-Yang ZHU (SKLCS, Beijing)
===== Submission Guidelines =====
We invite authors to submit 2 – 4 page extended abstracts, in double column format, font no smaller than 10 points. A booklet containing the proceedings will be available at the conference and on the website of the workshop. Templates are available at:
Authors may submit their work using the following link:
Accepted submissions will be invited to give either a long 25 minute presentation or a short 15 minute presentation depending on the content of the submission as seen fit by the program committee.