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IDT 2013 : 8th IEEE International Design and Test Symposium

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Link: http://idt.tttc-events.org
 
When Dec 16, 2013 - Dec 18, 2013
Where Marrakesh, Morocco
Submission Deadline Sep 30, 2013
Notification Due Oct 30, 2013
Final Version Due Nov 15, 2013
Categories    design automation   embedded systems   design automation   test
 

Call For Papers

==============================================
CALL FOR PAPERS

IEEE IDT 2012
8th IEEE International Design and Test Symposium

Marrakesh, Morocco
December 16- 18, 2013

http://idt.tttc-events.org
==============================================

Important Dates
-----------------------
Submission deadline : Sept 30
Notification : October 30
Camera-Ready : November 15


Call for Papers
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The International Design and Test Symposium explores emerging challenges and novel concepts in design, automation, test and reliability of electronic products ranging from integrated circuits through multi-chip modules and printed circuit boards to full systems and microsystems. IDT provides unique forum to discuss best practices and novel ideas in design methods, tools, test and reliability in the Middle East and Africa (MEA) region. IDT’13 will take place in Marrakesh, Morocco. The Symposium is initiated by and in affiliation with the IEEE Test Technology Technical Council (TTTC) and the 2013 edition is organized by The Delft University of Technology and technically sponsored by IEEE CEDA (Council on Electronic Design Automation). The official language of the conference is English.

Manuscripts describing original work on any topic from the scope of IDT are welcome. Authors are asked to submit technical papers in accordance to the author’s instructions in one of the following two conference tracks, and topics of interest include but are not limited to:


Design Methods and Tools
SOC, SIP, NOC design
Multiprocessor systems
Embedded systems
Analog, Mixed Signal and RF systems
MEMS and MOEMS systems
Low Voltage and Low Power syst.
Innovative technologies
Real time systems
Simulation, Validation & Verification
System Specification and Modelling
Formal Methods and Verification
System Design/Synthesis/Optimization

Test and Reliability
SOC and SIP testing
Multiprocessor test
Memory & FPGA Test & repair
Delay testing
Analog and Mixed Signal testing
MEMS/MOEMS testing
Defect and fault modeling
DFT, BIST and BISR
On-line testing / fault tolerant syst.
Fault Simulation, ATPG
Reliability failures/ modeling
Circuit reliability
Electronic system reliability


Best Regards,
On behalf of the organizing committee,
2013 IEEE International Design and Test Symposium

General Co-Chairs
Said Hamdioui, TU Delft (NL)
Yervant Zorian, Synopsys (USA)

Vice General Co-Chairs
Andre Ivanov, UBC (CA)
Hazem ElTahawy, Mentor (EG)

Program Co-Chairs
Drechsler, University of Bremen/ DFKI (GE)
Paolo Prinetto, Polito (IT)
Ashraf Salem, Mentor Graphics (EG)

Vice Program Co-Chairs
Mazen A. R. Saghir, Texas A&M University at Qatar (QA)
Smail Niar, U Valenciennes (FR)

Publicity Chairs
Bernard Courtois, CMP (FR)
Ozgur Sinanoglu, NY Uni (UAE)

Special Session Co-Chairs
Matteo Sonza Reorda, Polito (IT)
Rafik Makki, Global Foundries (USA)

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