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ICCAD 2013 : The International Conference on Computer-Aided Design


Conference Series : International Conference on Computer Aided Design
When Oct 28, 2013 - Oct 31, 2013
Where San Jose, CA, USA
Abstract Registration Due Apr 1, 2013
Submission Deadline Apr 8, 2013
Categories    design automation

Call For Papers

Original technical submissions on, but not limited to, the following topics are invited:

1.1 System Design:
• System-level specification, modeling, and simulation
• System design flows and methods
• HW/SW co-design, co-simulation, co-optimization, and co-exploration
• HW/SW platforms
• Rapid prototyping
• System design case studies and applications
• System-level issues for 3D integration
• Micro-architectural transformation
• Memory architecture and system synthesis
• System communication architecture
• Network-on-chip design methodologies and CAD
• Network-on-chip design case studies and prototyping
1.2 Embedded Systems Hardware: • Multi-core/multi-processors systems
• Heterogeneous embedded architectures
• HW/SW co-design for embedded systems
• Static and dynamic reconfigurable architectures
• Memory hierarchies and management
• Custom storage architectures (flash, phase change memory, STT-RAM, etc.)
• Application-specific instruction-set processors (ASIPs)
• Cyber-physical system architectures
1.3 Embedded Systems Software:
• Real-time software and operating systems
• Middleware and virtual machines
• Timing analysis and WCET
• Programming models for multi-core systems
• Profiling and compilation techniques
• Design exploration, synthesis, validation, verification, and optimization
• HW/SW security techniques
• Software for cyber-physical systems
1.4 Power and Thermal Considerations in System Design:
• Power and thermal estimation, analysis, optimization, and management techniques for hardware and software systems

2.1 High-Level, Behavioral, and Logic Synthesis and Optimization:
• High-level/Behavioral/Logic synthesis
• Technology-independent optimization and technology mapping
• Functional and logic timing ECO
• Resource scheduling, allocation, and synthesis
• Interaction between logic synthesis and physical design
2.2 Validation, Simulation, and Verification:
• High-level/Behavioral/Logic modeling and validation
• High-level/Behavioral/Logic simulation
• Formal, semi-formal, and assertion-based verification
• Equivalence and property checking
• Emulation and hardware simulation/acceleration
• Post-silicon functional validation
2.3 Cell-Library Design, Partitioning, Floorplanning, Placement:
• Cell-library design and optimization
• Transistor and gate sizing
• High-level physical design and synthesis
• Estimation and hierarchy management
• 2D and 3D partitioning, floorplanning, and placement
• Post-placement optimization
• Buffer insertion and interconnect planning
2.4 Clock Network Synthesis, Routing, and Post-Layout Optimization and Verification:
• 2D and 3D clock network synthesis
• 2D and 3D global and detailed routing
• Package-/Board-level routing and chip-package-board co-design
• Post-layout/-silicon optimization
• Physical verification and design rule checking

3.1 Design for Manufacturability:
• Process technology characterization, extraction, and modeling
• CAD for design/manufacturing interfaces
• CAD for reticle enhancement and lithography-related design
• Variability analysis and statistical design and optimization
• Yield estimation and design for yield
3.2 Design for Reliability:
• Analysis and optimization for reliability issues (thermal, electromigration, aging, stress, ESD, etc.)
• Design for resilience and robustness
• Soft errors
3.3 Testing:
• Digital fault modeling and simulation
• Delay, current-based, low-power test
• ATPG, BIST, DFT, and compression
• Memory test and repair
• Core, board, system, and 3D IC test
• Post-silicon validation and debug
• Analog, mixed-signal, and RF test

4.1 Timing, Power, and Power Networks:
• Deterministic and statistical static timing analysis and optimization
• Power and leakage analysis and optimization
• Low power design
• Power/ground network analysis and synthesis
4.2 Signal Integrity and Devices/Interconnect Modeling and Simulation:
• Signal integrity analysis and optimization
• Package modeling, analysis, and optimization
• EMI/EMC simulation and optimization
• Device, interconnect, and circuit modeling, extraction, and simulation
• Behavioral modeling of devices and circuits
4.3 Analog, Mixed-Signal, RF and Multi-Domain Design and CAD:
• System-level issues for analog, mixed-signal, and RF designs
• Synthesis and verification for analog, mixed-signal, and RF designs
• Device modeling and simulation for analog, mixed-signal, and RF designs
• Layout for analog, mixed-signal, and RF designs
• CAD for mixed-domain (semiconductor, nanoelectronic, MEMS, and electro-optical) devices, circuits, and systems

5.1 Biological Systems and Bio-Electronics:
• CAD for biological computing systems
• CAD for system and synthetic biology
• CAD for bio-electronic devices, sensors, MEMS, and systems
5.2 Nanoscale and Post-CMOS Systems:
• New device structures and process technologies
• New memory technologies (flash, phase change memory, STT-RAM, memristor, etc.)
• Nanotechnologies, nanowires, nanotubes, graphene, etc.
• Quantum computing
• Optical devices and communication
5.3 Design and Optimization for New Electronics and Applications
• Green computing (smart grid, energy, solar panel, etc.)
• Display electronics
• Automobile electronics and eMobility
• Sensors and sensor networks
• Design case studies for multimedia, communication, and consumer electronic applications
• Data Centers

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