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VLSICS 2023 : International journal of VLSI design & Communication Systems


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Where N/A
Submission Deadline Dec 2, 2023
Notification Due Dec 23, 2023
Final Version Due Dec 29, 2023

Call For Papers

International Journal of VLSI design & Communication Systems (VLSICS)

Citations, h-index, i10-index of VLSICS

Citations 2484   h-index 25   i10-index 75

Scope and Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas. Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include but are not limited to, the following

  • Design
  • VLSI Circuits
  • Computer-Aided Design (CAD)
  • Low Power and Power Aware Design
  • Testing, Reliability, Fault-Tolerance
  • Emerging Technologies
  • Post-CMOS VLSI
  • VLSI Applications (Communications, Video, Security, Sensor Networks, etc)
  • Nano Electronics, Molecular, Biological and Quantum Computing
  • Intellectual Property Creating and Sharing
  • Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through Email: or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates


Submission Deadline:December 02, 2023
Authors Notification: December 23, 2023
Final Manuscript Due: December 29, 2023
Publication Date:Determined by the Editor-in-Chief

Current Issue

April 2023, Volume 15, Number 2

Mighty Macros and Powerful Parameters: Maximizing Efficiency and Flexibility in HDL Programming Full Text
Muneeb Ulla Shariff, Vineeth Kumar Veepuri, Nancy Dimri and Mahadevaswamy B N, Mirafra Technologies, India

An Efficient Segmented Random Access Scan Architecture with Test Compression Full Text
Maddumage Karunaratne1 and Bejoy G. Oomman2, 1University of Pittsburgh, USA, 2Genesys Testware/Broadcom Inc., USA

Related Journal

Associate Editors

Editorial Board Members

... More

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