The International Workshop on Logic and Synthesis provides a forum for research in synthesis, optimization, and verification of integrated circuits and systems. The emphasis is on novelty and intellectual rigor. The workshop encourages early dissemination of ideas and results. The workshop format includes paper presentations, posters, invited talks, social lunch and dinner gatherings, and recreational activities.

Topics of interest include (but are not limited to):

* synthesis and optimization;
* power and timing analysis;
* testing and verification;
* architectures and compilation;
* design experiences.

Research on modeling, analysis and synthesis for emerging technologies and platforms is particularly encouraged. The workshop accepts complete papers as well as abstracts, highlighting important new problems in the early stages of development, without providing complete solutions.

The workshop is being held at Granlibakken Lodge in Lake Tahoe, California.
Paper Submission

Paper submission is open through EDAS.

Login into the system (create an account for yourself, if you haven't used it before.) Choose the "Submit Paper" tab; find IWLS'08; and click on the paper-and-pencil icon on the right-hand side.

Both complete papers as well as extended abstracts highlighting new problems and new topics of research are welcomed. (Only original and previously unpublished material is permitted.) Submissions must be no longer than 8 pages, double column, 10-point font. Accepted papers are distributed only to IWLS participants.
Dates

Submission of papers: Extended to March 23, 2008 (midnight EST)
Notification of acceptance: April 6, 2008
Final version due: April 23, 2008
Programming Challenge

The workshop includes a programming challenge. Students compete in the implementation of logic optimization algorithms with the OpenAccess Gear infrastructure. Travel grants and cash prizes are awarded for significant contributions. For more information, see the programming challenge home page.

Benchmarks

The IWLS community maintains a set of benchmarks, synthesized and mapped in Verilog and OpenAccess.
Organizing Committee

General Chair Marc Riedel University of Minnesota
Technical Program Chair Sunil Khatri Texas A & M University
Special Sessions Chair Valeria Bertacco University of Michigan
Publications Chair Igor Markov University of Michigan
Special Activities Chair Alan Mishchenko University of California, Berkeley
Programming Challenge Chairs
Christoph Albrecht Cadence
Florian Krohm IBM