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INA-OCMC 2013 : 7th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip


When Jan 23, 2013 - Jan 23, 2013
Where Berlin, Germany
Submission Deadline Oct 31, 2012
Notification Due Nov 30, 2012
Categories    noc   interconnects   networks

Call For Papers


Interconnection Network Architectures: On-Chip, Multi-Chip
co-located with HIPEAC conference 2013, Berlin, Germany

When interconnecting different end-nodes in on-chip and multi-chip processing
architectures, the communication infrastructure plays a dominant role in
determining overall system metrics such as performance, reliability and often
even area and power. On the other hand, each application domain poses its
own design constraints that the interconnect fabric has to cope with, thus
leading to well differentiated architecture design principles. Ultimately,
careful engineering of the interconnection network is at the core of the
successful development of both on-chip and multi-chip processing architectures.

The program of the workshop is organized around two main directions.
The first direction includes original papers describing new and previously
unpublished results on all aspects of interconnection network architectures.
Topics of interest include but are not limited to:

* Networks-on-Chip (NoC)
* Multi-Chip Interconnection Networks, including Cluster Interconnects
* "Commodity Switches" as general-purpose building blocks
* Switching, buffering, and routing architectures
* Flow control and congestion management in switching fabrics
* Virtualization
* Topology exploration
* Timing, synchronous/asynchronous communication
* Reliability, availability, fault tolerance
* Area/power versus functionality/QoS support in NoC architectures
* NoC physical link design
* NoC testing and verification
* Programming models for NoC-centric systems

The second direction will be focused to the design and analysis of reconfigurable
Networks-on-Chip. Besides of the already known, hardwired interconnection networks,
this special session tries to identify possible new solutions to the area of
reconfigurable Networks-on-Chip that can better adapt to system's needs.
The main target of this session is to attract highly qualified submissions
that fall into the next three broad categories:

* Specifically designed network components that allow some form of static or
runtime programmability to their function, allowing for higher performance
under certain occasions or for additional fault tolerance.

* The mapping and implementation of NoCs to reconfigurable platforms (FPGAs)
as soft components and the implications that this mapping generates to the NoC

* On-demand network topologies and structures that better fit to the application
characteristics and algorithms.

Both regular papers and those submitted to the special session will be handled
in a unified manner by the Program Committee accepting only high-quality submissions.
The submission and the review process will be handled electronically via EasyChair

Papers must be in PDF format and should include title, authors and affiliations
as well as the e-mail address of the contact author. Papers must be formatted in
accordance to the ACM two-column style. ACM Word or LaTeX style templates will
be available on the website. Submissions must be limited to 4 pages.
Papers deviating significantly from the paper size and formatting rules may be
rejected without review.

Submission deadline: October 19th 2012
Author notification: November 30th 2012

Workshop Organizers

General Chairs:
* Davide Bertozzi (University of Ferrara, Italy)
* Cyriel Minkenberg (IBM Zurich Research Lab, Switzerland)

Program Chairs:
* Soeren Sonntag (Intel, Germany)
* Giorgos Dimitrakopoulos (Democritus University of Thrace, Greece)

Steering Committee:
* Jose Duato (Technical University of Valencia, Spain)
* Manolis Katevenis (FORTH, Greece)

Publication Chair:
* Alberto Ghiribaldi (University of Ferrara, Italy)

Publicity Chair:
* Frank Olaf Sem-jacobsen (Simula, Norway)

Technical Program Committee:
* Federico Angiolini, iNoCS, Switzerland
* Nikos Chrysos, IBM Research Zurich, Switzerland
* Marcello Coppola, ST, France
* Natalie Enright Jerger, University of Toronto, Canada
* Pedro Javier Garcia, University of Castilla-La Mancha, Spain
* Francisco Gilabert, Intel, Germany
* Kees Goosens, TU Eindhoven, Netherlands
* Emmanouil Kalligeros, University of the Aegean, Greece
* Janusz Kleban, Poznan University of Technology, Poland
* Philippe Martin, Arteris, France
* Hiroki Matsutani, Keio University, Japan
* Jose Angel Gregorio Monasterio, University of Cantabria, Spain
* Chrysostomos Nicopoulos, University of Cyprus, Cyprus
* Steven Nowick, Columbia University, USA
* Maurizio Palesi, Kore University, Italy
* Sven Arne Reinemo, Simula, Norway
* Jose Luis Sanchez Garcia, University of Castilla-La Mancha, Spain
* Federico Silla, Universidad Politécnica de Valencia, Spain
* Vassos Soteriou, Cyprus University of Technology, Cyprus
* Pascal Vivet, CEA, France
* Eitan Zahavi, Mellanox, Israel

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