posted by user: wimmer || 3097 views || tracked by 8 users: [display]

MTV 2012 : 13th International Workshop on Microprocessor Test and Verification

FacebookTwitterLinkedInGoogle


Conference Series : Microprocessor Test and Verification
 
Link: http://mtvcon.org/
 
When Dec 10, 2012 - Dec 13, 2012
Where Austin, TX, USA
Submission Deadline Sep 1, 2012
Notification Due Oct 15, 2012
Final Version Due Nov 10, 2012
Categories    verification   test   microprocessors
 

Call For Papers

Overview
The 13th annual workshop on Microprocessor Test and Verification will be held on December 10th through 13th, 2012 in Austin, TX.

General Chair: Magdy S. Abadir, Freescale Semiconductor
Program Co-Chair: Jay Bhadra, Freescale Semiconductor
Program Co-Chair: Li-C. Wang, University of California at Santa Barbara

Scope
The purpose of MTV is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 13th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross-examination of test and verification experiences and innovative solutions.

Areas of Interest include
Validation of microprocessors and SOCs
Experiences on test and verification of high performance processors and SOCs
Test/verification of multimedia processors and SOCs
Performance testing
High-level test generation for functional verification
Emulation techniques
Silicon debugging
Low Power verification
Formal techniques and their applications
Verification coverage
Test generation at the transistor level
Equivalence checking of custom circuits at the transistor level
ESL Methodology
Virtual Platforms
Software verification
Circuit level verification
Switch-level circuit modeling
Timing verification techniques
Path analysis for verification or test
Design error models
Design error diagnosis
Design for testability or verifiability
Optimizing SAT procedures for application to testing and formal verification

Related Resources

CAV 2021   33rd International Conference on Computer-Aided Verification
VTS 2021   39th IEEE VLSI Test Symposium
DATE 2021   Design, Automation and Test in Europe Conference
IJCSEA 2020   International Journal of Computer Science, Engineering and Applications
NFM 2021   13th NASA Formal Methods Symposium
QEST 2021   International Conference on Quantitative Evaluation of SysTems
ICST 2021   IEEE International Conference on Software Testing, Verification and Validation 2021
DATE 2020   Design, Automation, and Test in Europe
ISSTA 2021   International Symposium on Software Testing and Analysis
TACAS 2021   27th International Conference on Tools and Algorithms for the Construction and Analysis of Systems