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EESC 2012 : First international Workshop on Energy Efficiency in Supercomputing (EESC 2012)

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Link: http://eesc.in.tum.de
 
When Jun 29, 2012 - Jun 29, 2012
Where Venice
Submission Deadline Apr 16, 2012
Notification Due May 7, 2012
Final Version Due May 20, 2012
Categories    green computing   high performance computing   energy   parallel computing
 

Call For Papers

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** Extended Submission Deadline: April 16th 2012 **

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First international Workshop on
Energy Efficiency in Supercomputing (EESC 2012)
http://eesc.in.tum.de/


held in conjunction with

ICS 2012, San Servolo Conference Island/Venice/Italy
http://ics-conference.org/
June 2012


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One of the major challenges on the way towards exascale computing is the ever growing demand in electrical power and energy that HPC systems consume. The reasons are the ever growing number of transistors on the processors and the steep increase in the number of processors in order to accelerate the pace of HPC systems. The increased parallelism requires more system infrastructure (e.g., interconnect, memory, I/O nodes, and cooling) in order to harness most of the available compute power. This parallelism in turn leads to higher system power levels and energy consumption, which requires a bigger support infrastructure (e.g., building design, power supply, and cooling) to handle the increased power and cooling requirements.

The challenge that the HPC community faces in the next decade will be to reduce the power requirements on every level of HPC systems while still increasing compute performance. This workshop will provide a forum for researchers to present and to exchange ideas concerning power monitoring, modeling and saving methods for all levels of HPC.


Workshop Topics:
* Power-aware HPC architectures
* Models for power and performance aware optimizations (energy-to-solution)
* Profiling tools for power and performance
* Energy-efficient infrastructure: power, cooling, and energy recycling
* Energy-aware analysis techniques
* Power-aware networks in HPC
* Automatic energy tuning of single applications
* Energy saving methods in processors

The workshop is supported by AutoTune, an FP7 project (www.autotune-project.eu) that focuses on automatic performance and energy tuning.


Important Dates:
* April 16th: submission deadline (extended)
* May 7th: author notification
* May 20th: camera ready papers due
* June 29th: workshop

All submissions will undergo a review by at least two reviewers. We welcome submissions of full papers not exceeding 10 pages in Springer LNCS format presenting unpublished work which will be published in a workshop proceeding. The authors of the best papers will be invited to submit an extended version for a special issue of the Springer Computing Journal. See eesc.in.tum.de for more details.


Workshop chairs:
Arndt Bode, LRZ, Technische Universitaet Muenchen
Bronis R. de Supinski, Lawrence Livermore National Laboratory


Programm Committee:
Arndt Bode, LRZ Muenchen
Kirk Cameron, Virginia Tech
Karl Fuerlinger, LMU Muenchen
Michael Gerndt, Technische Universitaet Muenchen
Dieter Kranzlmueller, LMU Muenchen
Dong Li, Oak Ridge National Laboratory
David Lowenthal, University of Arizona
Dimitrios Nikolopoulos, Queen's University of Belfast
Alex Ramirez, Barcelona Supercomputing Center
Barry Rountree, Lawrence Livermore National Laboratory
Martin Schulz, Lawrence Livermore National Laboratory
Bronis R. de Supinski, Lawrence Livermore National Laboratory
Carsten Trinitis, Technische Universitaet Muenchen
Josef Weidendorfer, Technische Universitaet Muenchen


Organization Committee:
Petra Piochacz (petra.piochacz@in.tum.de), Axel Auweter (axel.auweter@lrz.de), Torsten Wilde (torsten.wilde@lrz.de)

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