IEEE DTTIS conference (International Conference on Design, Test and Technology of Integrated Systems)

Venue: Hammamet, Tunisia
Dates: November 4-6, 2026
Website: https://dttis2026.si2e.tn/

Aim of the Conference: IEEE DTTIS conference (International Conference on Design, Test and Technology of Integrated Systems) is the result of merging two established conferences: DTIS (International Conference on Design and Technology of Integrated Systems in nanoscale era), and DTS (International Conference on Design and Test of Integrated Systems).
The aim of the conference is to cope with the rapidly progressing technology which, today, reaches the nanometer scale. The areas of interest include design, test and technology of electronic products, ranging from integrated circuit modules, chiplets and printed circuit boards to full systems and microsystems, as well as the methodologies and tools used in the design, verification and validation of such products. IEEE DTTIS will show innovations in system and platform design, which extend beyond a single integrated circuit. These platforms may include 2.5D/3D chiplet based system-in-package, system-on-interposer, and multi-die integrations. It will be an opportunity for researchers to present and discuss their latest work. IEEE DTTIS is, by design, a forum for engineers, researchers, graduate students and professors, to cross the design-technology boundary by bringing design, test, technology, and process experts together.
IEEE DTTIS will be organized annually in a Mediterranean country. The 21st edition is scheduled to be held in Hammamet, Tunisia. All accepted and presented papers will be published on the IEEE DTTIS Conference Proceedings and submitted for publication in IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. Best papers will be submitted for possible publication in a special issue of Analog Integrated Circuits and Signal Processing Journal.
Papers are solicited in, but not limited to, the following topics:

Integrated Systems Design

Analog, digital, mixed, and RF circuits design
System-on-a-chip (SoC) & System of Chips (SoC), MPSoC, NoC, SIP, and NIP design
Embedded/ multiprocessor systems
Hardware design for AI
AI accelerators
MEMS, NEMS and MOEMS systems design
Synthesis (physical, logic,...)
Simulation, Validation & Verification
Bio-engineering & Bio-chip design
Electronics for energy harvesting
Wireless communication systems design
Opto-electronic System Design
Biomedical Circuit & Systems
Power electronics and systems design
Sensory Systems Design
Chiplet and disaggregation
Intelligent and Autonomous Robotic Systems
Embedded AI and TinyML
Real-time inference under power, latency, and memory constraints
Hardware–software co-design for intelligence at the edge
Multi-agent coordination and distributed intelligence
Heterogeneous computing platforms (CPU–GPU–FPGA–ASIC)
Interoperability across hardware, software, and networks
Hardware–software co-design for intelligence at the edge
Integrated Systems Testing

Defect and Fault Modeling
Analog, digital circuit test
Mixed, and RF circuit testing
MEMS/NEMS/MOEMS Testing
3D/2.5D Test
Memory test
Repair and diagnosis
Reliability
DFT, BIST and BISR
Alternatives test strategies
Fault Simulation, ATPG
Yield Optimization
Automotive reliability and test
Reliability failures and modeling
Electronic System Reliability
Test and Security Issues
ATE issues
On-line Testing and fault Tolerance
Delay testing
Integrated Systems Technology

Process technologies
Device modeling
Material characterization
Failure analysis
Emerging technologies
ICs Packaging
Process technology
Reliability issues
2.5 & 3D integration
Circuit integrity
Key Dates for Scientific Papers:

Abstract submission: May, 15th 2026
Paper pdf Submission Deadline: May, 20th 2026
Notification of acceptance: July, 01st 2026
Final version due date: July, 15th 2026
IEEE DTTIS’26 Plenary Session:

Keynote 1

Test and Diagnosis Challenges for High-Yield Manufacturing in the Ångström Era

Presenter:
Full name: Aymen Ladhar
Affiliation: Engineer at Intel, Ireland
Email: aymen.ladhar@intel.com
______________________________________________________________

Keynote 2

Low Power Challenges in IoT and IoE

Presenter:
Full name: Ricardo Reis
Affiliation: Instituto de Informática, Universidade Federal do Rio Grande do Sul, at Porto Alegre, Brazil
Email: reis@inf.ufrgs.br
______________________________________________________________

Keynote 3

Embodied AI for Next Generation Intelligent Systems

Presenter:
Full name: Fakhri Karray
Affiliation: University of Waterloo
Email: fkarray@gmail.com
IEEE DTTIS’26 Plenary Session:

Best papers will be submitted for possible publication in a special issue of the journal:

Analog Integrated Circuits and Signal Processing