VLSI Circuits 2012 : 2012 Symposium On VLSI Circuits
Call For Papers
The three days of the 2012 Symposium on VLSI Circuits will provide designers of integrated circuits an opportunity to
meet and present important new work on all aspects of VLSI circuits. The 2012 Symposium on VLSI Technology (please
see the reverse side) will be held at the same location with two days of overlap. A single registration allows participants
to attend both of the Symposia, and offers unique opportunities to interact and synergize on topics of joint interest.
The scope of the Symposium on VLSI Circuits includes innovations and advances in the following areas:
• RF and wireless communication circuits and architecture, including CMOS RF and mm-wave
• Wireline transceiver and I/O design, spanning chip-to-chip to long-reach applications
• Digital circuit techniques for processor, memory, and complex SOC architectures and implementations
• Clock generation and distribution for high frequency digital and mixed-signal applications
• Analog and mixed signal circuits such as data converters, PLL, amplifiers, and filters
• Digitally-assisted analog and analog-assisted digital circuits, including digital implementations of RF/analog
• Memory circuits and architectures for SRAM, DRAM, and non-volatile, including emerging memories
• Power minimization techniques, circuits for battery management, energy harvesting, and renewable energy
• Power management circuits, including linear and switching voltage regulators and voltage references
• Sensor and display circuits for current and emerging applications, including biomedical and healthcare.
NEW JOINT CIRCUITS AND TECHNOLOGY FOCUS SESSIONS
For the first time, joint circuit and technology focus sessions will be offered in the following special topics of joint interest.
Paper submissions highlighting major innovations and advances in circuits, designs, tools and methodologies in these
areas are strongly encouraged:
• Design in scaled technologies: novel device and interconnect materials and structures (e.g. FinFET, hybrid III-V,
nanotubes, nanowires), scaling of analog and mixed-signal design
• Design enablement: design for manufacturing and robustness, process-design co-optimization for ultra-low voltage and
power, on-die measurement and monitoring of variability and reliability
• Memory technology and design: embedded and stand-alone SRAM, DRAM, Flash, PCRAM, RRAM, MRAM, etc.
• 3D (TSV) and heterogeneous integration: power and thermal management, inter-chip communication, SiP
architectures and applications.
Papers will be considered on the basis of originality, innovation, and advancing the field. Prototype implementation and
measured results will be considered favorably in the ratings. Prospective authors must submit camera-ready papers in
the format of two pages to the following web site:
Please note that hard copy submissions will NOT be accepted. The papers, if accepted, will be published as
submitted. The technical content beyond the abstract of the accepted paper must not be announced, published, or in
any way put in the public domain prior to the Symposium. Submissions from industry and universities are encouraged.
Partial travel expense support for students who are presenting papers is available upon request. Extended versions of
selected papers from the Symposium will be published in a Special Issue of the IEEE Journal of Solid-State Circuits.