WRA 2011 : 2nd Workshop on Resilient Architectures (in conjuction with MICRO-2011)
Call For Papers
We cordially invite you to submit a paper to the 2nd Workshop on Resilient Architectures at Micro-2011. The aim of this workshop is to provide a platform for interdisciplinary lines of thought for enabling resilient architectures.
Please find below the call-for-papers for the workshop.
Workshop on Resilient Architectures (WRA) held in conjunction with MICRO-2011, Porto Algere, Brazil
How do we design error-tolerant processors (and associated systems) that meet historically established high reliability standards, without exceeding fixed power budgets and cost constraints? This is the technological research challenge that present day and future processor architects face. In the late CMOS era, device-scaling trends have resulted in an increased awareness of the various sources of unreliability at the component level. Designing and building robust processors is becoming increasing challenging in the face of growing device susceptibility to transient and hard errors. Some solutions, such as those that circumvent the power problem today, have in fact been shown to worsen conditions for the emerging new device reliability wall. Future systems will require processor architects to integrate adaptive design techniques, at both the device- and system-level, to ensure robust and resilient execution. The architecture layer, that includes both hardware and software, must learn to dynamically identify, detect and recover from errors in the field. To this end, the goal of this workshop is to act as a forum for both hardware and software architects to interact and discuss novel ideas that would enable the success of resilient architectures in the future. While we welcome innovation at the obvious architecture and circuits’ layers, we would like to strongly encourage the software community to participate in hardware resiliency.
Topics of Interest
Characterizing overheads and/or tradeoffs for resiliency techniques
Resilient circuit and memory design
Emerging process technology issues
Residue codes for arithmetic, error detection sequential, more robust circuit topologies
Case studies, applications and experience reports
Benchmarking metrics for reliability
Hardware and software co-design
Virtualization, compilers, binary translation techniques
Programming language support
Resilient design for large-scale systems
GPU and GPGPU-centric reliability
Architectural support for secure intrusion-tolerant systems
We welcome other topics of interest and are not limited to the above set of suggestions.
Submission deadline: Oct 14th 2011
Author notification: Oct 28th 2011
Vijay Janapa Reddi (University of Texas at Austin) (email@example.com)
Meeta S. Gupta (IBM T. J. Watson) (firstname.lastname@example.org)