Call for Participation

Power and temperature characteristics have become primary design constraints in current high-performance computing systems, and now dictate the fundamental characteristics of the computing system, such as peak performance and reliability. Prior techniques for energy efficiency often do not help, because power demand and temperature are often most severe under high loads, while energy efficiency primarily focuses on minimizing energy during periods of performance slack.

These considerations have wide-ranging impact on system architecture, from cores to chips, servers and datacenters. High-performance computing is expected to be severely power limited in the next decade, where the high data intensity in scientific computing environments creates unique challenges and opportunities. Power usage quickly reaches megawatts, and almost half of the power is required for cooling. Current trends indicate that not only do the power/thermal constraints get more severe with each generation; they also become more difficult to design for, due to the multi-disciplinary and cross-stack nature of the power/thermal phenomena.

In this tutorial we take an in-depth look at power/temperature limitations and their cross-stack implications from chip-level to datacenter design. We will focus on both state-of-the-art industry practices and academic studies for insights on the key challenges and potential solutions in high-performance computing environments.

Date and Place: Friday (half day), October 14th, 2011. Held in conjunction with PACT 2011

Organizers:
* Kevin Skadron, University of Virginia
* Jose E. Moreira, IBM Research - T.J. Watson
* Eren Kursun, IBM Research - T.J. Watson
* Wei Huang, IBM Research - Austin