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INA-OCMC 2012 : 6th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip


When Jan 22, 2012 - Jan 22, 2012
Where Paris, France
Submission Deadline Oct 14, 2011
Notification Due Nov 15, 2011
Categories    interconnection networks   network-on-chip   networks   interconnection

Call For Papers



6th International Workshop on
Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC)

Held in conjunction with
the 7th International Conference on High Performance Embedded Architectures
and Compilers (HiPEAC) (
in Paris, France, January 23rd, 2012


General Chairs
- Davide Bertozzi, University of Ferrara, Italy
- Tor Skeie, Simula Research Labs, Norway

Program Chairs
- Cyriel Mickenberg, IBM Zurich, Switzerland
- Giorgos Dimitrakopoulos, Univ. of West Macedonia, Greece

Publications Chair
- Alessandro Strano, University of Ferrara, Italy

Publicity Chair
- Gaspar Mora, Intel, USA

Special Session Chair
- Maurizio Palesi, Kore University, Italy

Steering Committe
- Jose Duato, Techn. University of Valencia, Spain
- Manolis Katevenis, FORTH-ICS, Greece

When interconnecting different end-nodes in both on-chip and multi-chip
processing architectures, the communication infrastructure plays a dominant
role in determining overall system metrics such as performance, reliability
and often even area and power. On the other hand, each application domain
poses its own design constraints that the interconnect fabric has to cope
with, thus leading to well differentiated architecture design principles.
Ultimately, careful engineering of the interconnection network is at the core
of the successful development of both on-chip and multi-chip processing

Original papers describing new and previously unpublished results are
solicited on all aspects of interconnection network architectures.
Topics of interest include but are not limited to:

* Networks-on-Chip (NoC)
* Multi-Chip Interconn. Networks, including Cluster Interconnects
* "Commodity Switches" as general-purpose building blocks
* Switching, buffering, and routing architectures
* Flow control and congestion management in switching fabrics
* Virtualization
* Topology exploration
* Timing, synchronous/asynchronous communication
* Reliability, availability, fault tolerance
* Area/power versus functionality/QoS support in NoC architectures
* Design space exploration
* NoC physical link design
* NoC testing and verification
* Programming models for NoC-centric systems

Submissions from EU projects in progress as well as seminal work and new ideas
to stimulate advances in the field are also encouraged. The program committee
recognizes that such papers may contain fewer experimental results than papers
in established areas.

Paper submission:

Electronic paper submission requires a full paper, up to 4 double-column
ACM format pages, including figures and references. Please use the following
template when preparing your manuscript:
Papers should include title, authors and affiliation. The work will be
evaluated by the program committee based on scientific merit, innovation,
relevance, and presentation. The submission procedure will be through the
EasyChair web-page (
Accepted papers will be published in the ACM digital library.

Important dates:

Submission deadline: Extended to October 14th, 2011 (Previous was October 5th, 2011).
Notification of acceptance: November 15th, 2011.
Workshop: January 22rd, 2012

Technical Program Committee:

- Federico Silla, UPV, Spain
- Sudhakar Yalamanchili, Georgia Tech, USA
- Federico Angiolini, iNOCS, Switzerland
- Maurizio Palesi, Kore University, Italy
- Eitan Zahavi, Mellanox, Israel
- Janusz Kleban, Poznan University of Technology, Polland
- Kees Goosens, TUE, Netherlands
- Marcello Coppola, ST, France
- Pedro Javier Garcia, UCLM, Spain
- Jose Angel Gregorio Monasterio, Univ. of Cantabria, Spain
- Jose Luis Sanchez Garcia, UCLM, Spain
- Partha Kundu, Juniper Networks, USA
- Paco Gilabert, UPV, Spain
- Vassos Soteriou, CUT, Cyprus
- Natalie Enright Jerger, Univ. of Toronto, Canada
- Paul Ampadu, Univ. of Rochester, USA
- Steven Nowick, Columbia University, USA
- David Atienza, EPFL, Switzerland
- Nikos Chrysos, IBM Research Zurich, Switzerland
- Soeren Sonntag, Intel Mobile Communications, Germany
- Jaan Raik, Tallin University of Technology, Estonia
- Hiroki Matsutani, Keio University, Japan
- Pascal Vivet, CEA, France
- Ulrich Bruening, Univ. of Heidelberg, Germany
- Sven Arne Reinemo, Simula, Norway

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