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PATMOS 2011 : International Workshop on Power And Timing Modeling, Optimization and Simulation

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Conference Series : Power and Timing Modeling, Optimization and Simulation
 
Link: http://patmos.dacya.ucm.es/
 
When Sep 26, 2011 - Sep 29, 2011
Where Madrid, Spain
Submission Deadline May 15, 2011
Notification Due Jun 30, 2011
Final Version Due Jul 15, 2011
Categories    modeling   design automation   circuits   systems
 

Call For Papers

The PATMOS objective is to provide a forum to discuss and investigate emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGA’s. The technical program will focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization. The emphasis of the workshop is on, but not limited to, the following topics:

Timing and Performance
Methodologies and tools for the analysis, design and verification of timing and performance properties of integrated circuits and systems at all levels of abstraction;
Variability and statistical timing analysis;
Design for yield, design for manufacturability;
Special timing or performance related topics, e.g. crosstalk, synchronization, GALS, side-channel attacks.

Low Power and Thermal-aware Design
Design techniques for low power circuits and systems at all levels of abstraction;
Methods and tools for analysis and characterization of power consumption;
Power Estimation and Optimization;
Low power Architectures and System level Techniques;
Special power related topics, e.g. low voltage, leakage power, power grid, interconnect power, clock tree power, power aware test pattern generation, green computing;
Thermal-aware circuit and system design;
Polices for thermal optimization;
Temperature estimation and thermal sensors.

Reliability and Technology Variations
Modeling and simulation in the presence of on-chip variability;
Variation-aware circuit design;
Reliability issues in nanoscale circuits;
Soft errors and radiation hardening;
Fault tolerance and dependability;
Resilient circuits.

Power and Timing Issues Addressing Specific Technologies
Reconfigurable Architectures
Caches and Memory Devices.
Emerging Memory Technologies, e.g. Phase Change Memories

Design Experience and Case Studies
Examples, test cases, benchmarks or design studies which present innovative solutions for timing, performance or power consumption related design challenges.

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