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a4mmc 2011 : 2nd Workshop on Applications for Multi- and Many-Core Processors


When Jun 4, 2011 - Jun 8, 2011
Where San Jose, CA
Submission Deadline Apr 4, 2011
Notification Due Apr 29, 2011
Final Version Due May 15, 2011

Call For Papers

* A4MMC: 2nd Workshop on Applications for Multi- and Many-Core Processors *
* ( *
* held in conjunction with ACM/IEEE ISCA 2011 *
* ( *
* co-organized by Delft University of Technology and VU University Amsterdam *

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The Applications for Multi and Many Cores Processors (A4MMC) workshop,
held in conjunction with the 38th International Symposium on Computer
Architecture (ISCA), focuses on application case studies. With A4MMC,
we aim to provide a forum where multi and many core application
designers can exchange knowledge, insights and discoveries, and
discuss their latest research advances. Further, by collocating A4MMC
with ISCA, we aim to directly expose the software community's
findings, requirements, and problems to a select audience of top
computer architecture researchers. We believe we offer an ideal
opportunity for software and hardware researchers to communicate and
debate on how to find the right balance between these two sides of the
"multi-core revolution".

We encourage authors working on all aspects of applications for
multi/many core platforms to submit their unpublished research work.
The topics of particular interest include, but are not limited to:
* Applications and algorithms case-studies
+ Application implementation and optimization on MMCPs
+ Evaluation and/or implementation of new algorithms on MMCPs
+ Porting and parallelization strategies
+ MMCP-aware algorithms

* Programming Models and Tools
+ Evaluations of "classical" parallelization paradigms on MMCPs
+ Evaluations of existing MMCP programming models
+ Comparisons of application implementations using different MMCP
programming models
+ Compilers, debuggers, profilers

* Performance and Power Analysis
+ Methodologies, Metrics, and Benchmarking
+ Comparative studies of MMCPs architectures, focusing on
performance, efficiency, and/or power-consumption
+ Evaluating and tuning application power-footprints
+ Power-efficient MMCP algorithms

We invite two types of submissions:

Full papers
Not to exceed 12 pages in LNCS format, providing application
analysis, a presentation of the used algorithms and specific design or
implementation techniques, as well as the performance evaluation
and/or analysis of the application on the target platform(s). Ideally,
papers will also indicate essential requirements and/or useful
features that should be included in the next generation of hardware
for improving application performance, platform efficiency, and/or
programming productivity.

Short papers
Not to exceed 4 pages (plus 1 additional page only used for
bibliography/annexes) in LNCS format, discussing work in progress for
interesting applications. Application analysis and promising
parallelization strategies/techniques/models should be included.
Preliminary performance results are appreciated, but not mandatory.

For any accepted paper, at least one author is expected to attend the
workshop and present the paper. The A4MMC organizers investigate
opportunities to publish the workshop post-proceedings in a LNCS joint
volume with several ISCA workshops or in a special journal issue. More
information will be posted, as it becomes available, on the workshop

Important dates
The deadline for both full and short papers is April 4th, 2011,
23:59:59 PM CET (check for other time
zones). Author notifications are due on April 29th, 2011, and the
final versions of accepted papers are expected not later than May
15th, 2011.

Workshop Program Committee
Rosa Badia, Barcelona Supercomputing Center, Spain
Xavier Martorell, Universitat Politecnica de Catalunya, Spain
Jorg Keller, FernUniversität Hagen, Germany
Paul Kelly, Imperial College of London, UK
Cristoph Kessler, Linköping University, Sweden
Anton Lokhmotov, ARM, UK
Michael Perrone, IBM TJWatson Research Center, US
John Romein, ASTRON, The Netherlands
Sally McKee, Chalmers, Sweden
Yoav Etsion, Barcelona Supercomputing Center, Spain
Virat Agarwal, UBS, UK
Raymond Namyst, University of Bordeaux, France
David Bader, GeorgiaTech, USA

For additional questions or information requests, please contact the
organizing committee (

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