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MSPC 2011 : ACM SIGPLAN Workshop on Memory Systems Performance and Correctness 2011

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Link: http://www.cs.wm.edu/~xshen/MSPC11/
 
When Jun 5, 2011 - Jun 5, 2011
Where San José, California, USA
Abstract Registration Due Mar 18, 2011
Submission Deadline Mar 28, 2011
Notification Due Apr 28, 2011
Final Version Due May 12, 2011
Categories    compilers   programming languages   computer architecture   parallel computing
 

Call For Papers

(This workshop will be held in conjunction with PLDI/FCRC 2011.)
Despite the capped growth of the peak CPU speed in CMP, the memory wall problem becomes more serious and complex as more CPU/GPU cores are added, and the bandwidth resource becomes managed by multiple memory controllers and influenced by the constant cache interference among applications. Continuing the previous five successful workshops, MSPC 2011 will provide a forum for publishing and discussing the implications of the changes to both memory performance and correctness on various multi- and many-core systems---from supercomputers to servers to mobile devices---and the related software and hardware innovations. Areas of interest include but are not limited to the following topics:

•Analysis of memory systems performance (including power, bandwidth, and latency)
•Static and dynamic techniques for understanding and improving memory performance
•Memory hierarchy design for chip multiprocessors (CMPs)
•Hardware and software techniques for ensuring memory safety and detecting memory-related bugs (e.g., memory leaks, dangling pointers, out-of-bounds memory accesses, invalid C pointer arithmetic)
•Hardware and software memory models and their impact on programmability and performance
•Data race detection and debugging of programs with (possibly intentional) data races
•Managed memory and garbage collection optimizations
•Prefetching and compression to improve memory system performance
•Memory issues in accelerator-based computing (e.g., GPGPU)
•Memory system issues in embedded computers and tiny devices
•Impact of new storage class memory technologies (e.g., PCM, MRAM)
•Specifications of programming language (and library) shared memory semantics
•Power management and the impact on correctness/reliability
Software, hardware, and hybrid approaches are encouraged.

In addition, we solicit papers from practitioners describing problems and experiences with memory performance and correctness in specific application domains.

Submission Guidelines
We encourage the submission of not-fully-polished but provocative short position papers (6 pages) or position abstracts (1-2 pages). Authors should use standard ACM SIGPLAN conference format (10pt) and submit through the conference submission link. Copies of accepted papers will be made available at the workshop and published in the ACM digital library. Submitted papers must not be simultaneously under review for any other conference or journal, and authors should point out any substantial overlap with their previously published or currently submitted work.

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