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DSD 2011 : 14th Euromicro Conference On Digital System Design: Architectures, Methods and Tools


Conference Series : Digital Systems Design
When Aug 31, 2011 - Sep 2, 2011
Where Oulu, Finland
Submission Deadline Mar 21, 2011
Notification Due Apr 24, 2011
Final Version Due May 29, 2011
Categories    digital circuits and vlsi   microarchitectures   embedded   mixed hardware/software

Call For Papers

Architectures, Methods and Tools
Oulu, Finland, August 31 – September 2, 2011


- Submission of papers: EXTENDED UNTIL March 21, 2011
- Notification of acceptance: April 24, 2011
- Camera ready papers: May 29, 2011

“Due to an extraordinary situation in several countries (e.g. Japan) an additional extension is possible on request.”


The Euromicro Conference on Digital System Design (DSD) addresses all aspects of (embedded, pervasive and high-performance) digital and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It is a discussion forum for researchers and engineers from academia and industry working on state-of-the-art investigations, development and applications. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU and platform based system design research results are welcome. Design and Verification Languages and Standards, High Level Synthesis, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Asynchronous Techniques, Reconfigurable Architectures, Power Consumption, Computational Power Speed and Performance, Productive Design Technology and Engineering Flows, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues, Modeling, Design Experiences are covered in DSD.
The IEEE Conference Publishing Services (CPS), publishes the DSD Proceedings, which are available worldwide through the IEEE Xplore Digital Library. An extended version of the best papers will be published in a special issue of the ISI-indexed Microprocessors and Microsystems: Embedded Hardware Design journal, printed by Elsevier.


T1: (SHES) - System, hardware and embedded software design and automatic synthesis: high-level, behavioral, register-transfer, logic and physical circuit synthesis; arithmetic, signal processing and vector processing units; graphics processing units and hardware accelerators; memory design; communication architecture and protocols; specific circuits and processors; multi-objective optimization observing power, performance, communication traffic, interconnect architecture, layout, technology, reliability, robustness, security, testability and other issues; management of parallel computational resources, memory allocation and hierarchy; hardware/software co-design; mapping of applications to architectures; algorithm architecture matching; transaction level modeling and higher-level modeling; virtual system prototyping; design space exploration; synthesis of asynchronous and dataflow driven systems, nanoelectronics; CAD for placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification; CAD for modeling, analysis and optimization of timing and power..

T2: (SoC & NoC) - Systems-on-a-chip and networks-on-a-chip: multiprocessor systems on-a-chip (MPSoC), generic system platforms and platform-based design; CMP, SMP, SMT, DSP, VLIW and ASIP (multi)processor architectures and enhancements; 3D MPSoCs; software design and programming models for multicore platforms; benchmarks; GPUs; cell-based platforms; NoC architectural issues, quality of service in NoCs; 3D NoCs; power dissipation and energy issues in SoCs and NoCs; IP design, standardization and reuse; parallelism and scalability techniques; virtual components; system on a system; compiler assisted MPSoC; hardware support for embedded kernels; embedded software features; static, run-time and dynamic optimizations of embedded systems.

T3: (RC) - Programmable/re-configurable/adaptable architectures: design methodologies and tools for reconfigurable computing, run-time, partial and dynamic reconfigurability; fine-grained, mixed-grained and coarse-grained reconfigurable architectures; reconfigurable interconnections and NoCs; FPGAs; systems on re-configurable chip; system FPGAs and structured ASICs and co-processors; processing arrays; programmable fabrics; novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.); adaptive computing devices, systems and software; adaptable ASIPs and ASIP-based SOCs, hardware accelerators; optimization of FPGA-based cores; shared resource management; novel design algorithms for FPGA features; high-level models and tools for FPGAs; rapid prototyping systems and platforms; wireless and mobile systems.

T4: (SMVT) - System, hardware and embedded-software specification, modeling, verification and test: design, modeling, simulation and verification languages; functional, structural and parametric specification and modeling, model-based design and verification; system, hardware, and embedded software analysis; simulation, emulation, prototyping, formal verification, design-for-test and testing at all design levels; dependability and fault-tolerance issues.

T5: (APP) - Applications of (embedded) digital systems: emphasis on design challenges posed by demanding and new applications in fields such as: (wireless) communication and networking; networked electronic media, multimedia and ambient intelligence; image and video processing; mobile systems; health-care and medicine; ubiquitous, wearable and implanted systems; military, space, avionics, measurement, control and automotive applications; wireless sensor network applications; surveillance and security; environmental, agriculture, urban, building, transportation, traffic, energy, hazards and disasters monitoring and control.

T6: (ET) - Important issues introduced by emerging technologies: issues for the system, circuit and embedded software design introduced by e.g. the nanometer CMOS and beyond CMOS technologies, 3D integration, optical and new memory technologies etc.; new human-machine interfaces, neural- and bio-computation, (bio)sensor and sensor network technologies, pervasive and ubiquitous computing, 'internet of things'; design methods and EDA tools for solving these issues.


? SS1: (FDR) - Flexible Digital Radio.
? SS2: (MSDA) - Multicore Systems: Design and Applications.
? SS3: (DTDS) - Dependability and Testing of Digital Systems.
? SS4: (FTDSD) - Fault Tolerance in Digital System Design.
? SS5: (SLEO) - System-Level Energy Optimization of HW/SW Embedded Systems.
? SS6: (WSN) - Wireless Sensor Networks.
? SS7: (AHSA) - Architectures and Hardware for Security Applications.
? SS8: (M2APS) - Monitoring Methods for Adaptive Parallel Systems.

More information on special sessions:


Regular Papers: Prospective authors are encouraged to submit their manuscripts for review electronically through the following web page ( or by sending the paper to the Program Chair via email (, only if an unexpected web access problem is encountered) before the deadline for submission. Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the required IEEE format: single-spaced, double column, A4/US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the submitted manuscript, references included.

Case Studies and Application Papers: Submissions can be made which report on state-of-the-art digital systems, digital designs, architectures, design methods and/or tools, and (embedded) applications. Papers discussing lessons learned from practical experience, demanding or new applications, and experimental research are particularly encouraged. Manuscripts may be submitted in the same way as regular papers.


Chairman: Lech Jozwiak, Eindhoven U. of Tech. (NL)
Krzysztof Kuchcinski, Lund U. (SE)
Antonio Nunez, IUMA/U. Las Palmas GC (ES)

Pekka Abrahamsson, University of Helsinki, (FI)

Program Chairman: Paris Kitsos, Hellenic Open Univ., (GR)
Deputy Program Chairman: Smail Niar, U. Lille North France, Valencienne, (FR)

Chair: Pasi Kuvaja, University of Oulu, (FI)


A. Akkas, St. Cloud State U., (US)
A. Lastovetsky, University College Dublin, (IR)
A. Nunez, IUMA/U. of Las Palmas G.C., (ES)
A. Orailoglu, U. of California, San Diego, (US)
A. Pawlak, ITE & SUT, (PL)
A. Postula, U. of Queensland, (AU)
A. Shrivastava, Arizona State U., (US)
B. Juurlink, TU Berlin (DE)
C. Bouganis, Imperial College, (UK)
C. Cornelius, U. of Rostock, (DE)
C. Wolinski, IRISA, Rennes, (FR)
D. Houzet, Grenoble Institute of Technology, (FR)
D. Noguet, Minatec CEA-LETI, (FR)
D. Quaglia, U. of Verona, (IT)
E. Martins, U. of Aveiro, (PT)
F. Leporati, U. of Pavia, (IT)
G. Danese, U. Of Pavia, (IT)
H. Basson, U. of Littoral, (FR)
H. Kubatova, CTU Prague, (CZ)
H.T. Vierhaus, Brandenburg U. of Tech., (DE)
I. Hamzaoglu, Sabanci U., (TK)
J. Haid, Infineon Technologies, (AT)
J. Rabaey, U. of California, Berkeley, (US)
J. Sahuquillo, Pol. U. of Valencia, (ES)
J. Tiberghien, U. Libre de Bruxelles, (BE)
J.L. Dekeyser, U. of Lille, (FR)
J.S. Matos, U. of Porto, (PT)
K. Kent, U. of New Brunswick, (CA)
K. Kuchcinski, Lund U., (SE)
K. Popovici, Mathworks Inc., (US)
L. Benini, U. of Bologna, (IT)
L. Fanucci, U. of Pisa, (IT)
L. Jozwiak, Eindh. U. of Tech., (NL)
L. Sousa, U. of Lisboa, (PT)
L.-G. Chen, National Taiwan U., (TW)
M. Berekovic, TU Braunschweig (DE)
M. Figueroa, U. of Concepcion, (CL)
M. K. Michail, U. of Cyprus, (CY)
M. Perkowski, Portland St. U., (US)
M. Valero, Pol. U. of Catalunya, (ES)
M. Velev, Aries Design Automation, (US)
N. Dutt, U. of Calif., Irvine, (US)
N. Nedjah, State U. of Rio de Janeiro, (BR)
N. Sklavos, Tech. Inst. Patras, (GR)
O. Koufopavlou, U. Patras, (GR)
P. Carballo, IUMA/U. of Las Palmas GC, (ES)
P. Kitsos, Hellenic Open U., (GR)
P. Schumacher, Xilinx Inc., (US)
R. Drechsler, U. of Bremen, (DE)
R. Cumplido, INAOE, (MX)
R. Ubar, Tallinn Tech. U., (EE)
S. Kumar, Jonkoping U., (SE)
S. Lopez, IUMA/U. of Las Palmas G.C., (ES)
S. Niar, U. Valenciennes, (FR)
S. Vitabile, U. of Palermo, (IT)
T. El-Ghazawi, George Washington U., (US)
T. Luba, Warsaw U. of Tech., (PL)
T. Sasao, Kyushu Ins. of Tech., (JP)
V. Muthukumar, U. of Nevada Las Vegas, (US)
V. Prasanna, U. of Southern California, (US)
W. Luk, Imperial College, (UK)
W. Stechele, Technical U. Munich, (DE)
Y. Qu, Renesas Mobile, (FI)
Z. Kotasek, Brno U. of Tech., (CZ)

DSD permanent homepage is at:
US mirror:
Euromicro homepage is at:

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