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Micro - Compiling for Accelerators 2022 : IEEE Micro Special Issue on Compiling for Accelerators


When N/A
Where N/A
Submission Deadline Dec 15, 2021
Notification Due Mar 15, 2022
Final Version Due May 31, 2022
Categories    computer architecture   accelerators   compilers

Call For Papers

Hardware accelerators are rapidly becoming a central architectural feature to improve computation power performance. CPU ISA extensions, custom-designed engines, and FPGA-based systems have been proposed as acceleration architectures to improve program execution in scientific, machine-learning, database, and other application domains. Although much effort has been devoted to the design of accelerators, there is still a large gap of knowledge on how to make effective use of and compile for such architectures. As history has already taught us, having a great architecture is only half of the path to designing an efficient computing machine. Understanding the techniques required for quality code generation is central to the long-term establishment of an acceleration-based architectural paradigm.

This special issue of IEEE Micro will explore academic and industrial research on topics that relate to compiling for accelerators. Topics of interest include, but are not limited to:

- Compiling for CPU ISA extensions
- Code generation for neural processing units
- Compiling for neural network training
- Programming linear algebra engines
- Code generation and programming for database accelerators
- Processor-accelerator interface design and programmability
- Compiling for energy efficiency
- Pattern matching and code replacement for acceleration instructions
- High-level synthesis design of custom engines
- DSL and parallel programming models for accelerators
- Compiler intermediate representation (IR) and optimization techniques for accelerators
- Programming FPGAs for custom computing engines
- Tools and libraries to support code generation for accelerators

Important Dates
Submission Deadline: December 15, 2021
Initial notifications: March 15, 2022
Revised papers due: April 8, 2022
Final notifications: May 13, 2022
Final versions due: May 31, 2022
Publication: July/August 2022

Submission Guidelines
Please see the Author Information page and the Magazine Peer Review page for more information. Please submit electronically through ScholarOne Manuscripts, selecting this special-issue option.

For the manuscript submission, acceptable file formats include Microsoft Word (*) and PDF. Manuscripts should not exceed 5,000 words including references, with each average-size figure counting as 250 words toward this limit. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and email address) and a 200-word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication. Accepted articles will be edited for structure, style, clarity, and readability.

Contact guest editors Guido Araujo and Lucas Wanner at, or the editor-in-chief Lizy John at

Related Resources

OpenSuCo @ ISC HPC 2017   2017 International Workshop on Open Source Supercomputing
MICRO 2021   International Symposium on Microarchitecture
IJCSES 2021   International Journal of Computer Science and Engineering Survey
HEART 2021   11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
IJACEEE 2021   International Journal of Applied Control, Electrical and Electronics Engineering
CASES 2021   International Conference on Compilers, Architectures, and Synthesis for Embedded Systems
IJCSA 2021   International Journal on Computational Science & Applications
CogArch 2021   Fifth Workshop on Cognitive Architectures
DUAC 2021   International Workshop on Deployment and Use of Accelerators
COMMAG-FT-NanoNetworks 2021   IEEE Communications Magazine Feature Topic: Nano-Networking for Nano-, Micro-, and Macro-Scale Applications