International Journal of VLSI design & Communication Systems (VLSICS) Scope and TopicsInternational journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas.
Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications. Topics of interest include but are not limited to, the following - Design
- VLSI Circuits
- Computer-Aided Design (CAD)
- Low Power and Power Aware Design
- Testing, Reliability, Fault-Tolerance
- Emerging Technologies
- Post-CMOS VLSI
- Nano Electronics, Molecular, Biological and Quantum Computing
- Intellectual Property Creating and Sharing
- Wireless Communications
- VLSI Applications (Communications, Video, Security, Sensor Networks, etc)
- Microarchitecture Design
- Digital Integrated Circuits and Systems
- Biomedical Circuits and Healthcare Systems
- Electronic Design Automation
- Security and Privacy
- Emerging Technologies and new age Nano electronics
- Analog and Mixed-Signal Design/RF Circuit Design
- Embedded System Design and IoT
- Artificial Intelligence and Machine Learning
Paper SubmissionAuthors are invited to submit papers for this journal through Email: vlsicsjournal@airccse.org or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal. Important Dates | Submission Deadline | : | June 06, 2026 | | Authors Notification | : | June 25, 2026 | | Final Manuscript Due | : | June 29, 2026 | | Publication Date | : | Determined by the Editor-in-Chief |
June 2024, Volume 15, Number 1/2/3 Detection of Module Integration Errors in Hierarchical Circuit Designs
Nicholas Dematteis, Jesus Godinez, Gina Rhoads, and Maddu Karunaratne, University of Pittsburgh, USA Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs
V.Prasanth1, K.Babulu1, and M.Kamaraju2, 1JNTUGV, India, 2Gudlavalleru Engineering College, India April 2023, Volume 14, Number 1/2 Mighty Macros and Powerful Parameters: Maximizing Efficiency and Flexibility in HDL Programming
Muneeb Ulla Shariff, Vineeth Kumar Veepuri, Nancy Dimri and Mahadevaswamy B N, Mirafra Technologies, India An Efficient Segmented Random Access Scan Architecture with Test Compression
Maddumage Karunaratne1 and Bejoy G. Oomman2, 1University of Pittsburgh, USA, 2Genesys Testware/Broadcom Inc., USA December 2022, Volume 13, Number 1/2/3/4/5/6 Approximate Arithmetic Circuit Design for Error Resilient Applications
Viraj Joshi and Pravin Mane, Bits Pilani, K.K. Birla Goa Campus, Goa, India Related JournalAssociate EditorsEditorial Board Members - Amir Abbas Baradaran, Azad University and Payamenoor University, Iran
- Amitabha Sinha, Indian Institute of Engineering, Science & Technology, India
- Arman Roohi, University of Central Florida, FL, USA
- Asadollah Shahbahrami,University of Guilan, Iran
- Atena Abdi, Amirkabir University of Technology, Iran
- Barbaros Preveze, Cankaya University, Turkey
- Gayatri Mehta, University of North Texas, USA
- Hamid Ali Abed Al-asadi, Basra University, Iraq
- Hossein Khademolhosseini, Islamic Azad University, Iran
- Indranil Hatai, Indian Institute of Technology Kharagpur, India
- Intisar Al-Mejibli, University of Essex, United Kingdom
- Keivan Navi, Shahid Beheshti University, Iran
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