International Workshop on Data (Co-)Processing on Heterogeneous Hardware (DAPHNE)
colocated to EDBT/ICDT 2015, March 23-27, Brussels, Belgium

Website: daphne.uk.to

Call for Papers

Workshop Description

The goal of this one-day workshop is to investigate challenges and opportunities for data processing on existing and upcoming heterogeneous hardware architectures. Increased heterogeneity is one of the major current challenges in data processing on modern hardware. With multi-core CPUs, graphics cards, massively parallel accelerator cards (e.g. Intel Xeon Phi), heterogeneous mobile processors (e.g. ARM big.LITTLE) and FPGAs, we already face a huge variety of available processing devices with different capabilities, strengths and weaknesses. This trend is expected to accelerate in the near future, and tomorrow’s database systems will need to exploit and embrace this increased heterogeneity in order to keep up with the performance requirements of the modern information society.

The workshop intends to assist the formation and the growth of a community of researchers and industry practitioners that work on data (co-)processing problems on heterogeneous hardware. To this end, we want to provide a forum to discuss challenges, advances, and directions while also providing the right environment to network with people working on related topics and fostering future collaborations. The workshop solicits regular research papers describing preliminary and ongoing research results. In addition, the workshop encourages the submission of vision papers, novel ideas, and industrial experience reports of data co-processing. Furthermore, we also invite poster submissions to present data processing systems and applications – both commercial and research-oriented – that utilize heterogeneous hardware.
Topics

The scope of the workshop includes, but is not limited to:

- Applications of heterogeneous hardware in data mining, data-intensi ve machine learning and query processing.
- Algorithms and data structures for efficient data processing on (and across) co­processors (e.g., GPUs, APUs, accelerator cards, FPGAs).
- Efficient buffer management, data placement & data transfer strategies for heterogeneous hardware.
- Programming models and hardware abstraction mechanisms for writing data-intensive algorithms on heterogeneous hardware.
- Query optimization, cost estimation and operator placement strategies for coprocessors.
- Transaction processing on co­processors.
- Energy efficient data processing on co­processors (e.g. on ARM big.LITTLE).
- Algorithms and systems that utilize capabilities of modern processor architectures.


Important dates

- Submission deadline: December 22, 2014.
- Notification of acceptance: January 22, 2015.
- Camera-Ready submission deadline: January 29, 2015.
- Workshop: March 27, 2015


Submission and Review process

Papers can be submitted in two tracks: Regular research papers, and poster submissions. Research papers have a limit of eight pages (including references) and should present novel ideas, visionary thoughts, or new experimental evaluations for applications of coprocessors in data processing. If accepted, authors of research papers will be invited to give a 20 minute presentation during the workshop. Authors of poster submissions should prepare an extended abstract of at most two pages (including references). The abstract should summarize the content that will be presented on the poster (e.g., the system architecture, the application) and list relevant publications. Poster that provide insight into existing system are explicitly encouraged. If accepted, authors will be invited to provide a poster for the workshop’s poster session.

For submissions to both tracks, authors are requested to prepare their papers following the ACM double-column format using the template available at http://conferences.sigcomm.org/imc/2009/sig-alternate-10pt.cls. Papers will be uploaded as PDF files to the review system. Each paper will be reviewed by three PC members in a single-blind process.