7th WORKSHOP ON HETEROGENEITY AND MEMORY SYSTEMS (HMEM 2026)
Co-located with SC26, Chicago, IL, November 16, 2026

https://hmem-workshop.github.io

Overview and scope
====================

The 7th HMEM workshop serves as a forum to present and discuss ongoing research around heterogeneity and memory systems. The scope of the workshop encompasses all the layers of system and software stack, from computer architectures, operating system, middleware, programming models, runtime systems, tools, to applications.

Heterogeneity is ubiquitous, not only in terms of processing units but also memories and networks. As heterogeneity increases, memory subsystems play an even more important role to attain performance, from their technology to the system architecture to the software management and programming model. While CPU-only compute nodes are becoming rare instances, heterogeneous memory architectures have recently emerged and revolutionized the traditional memory hierarchy. Today’s and upcoming architectures may well comprise multiple memory technologies next to DRAM, accelerators with dedicated memories, or even specific expansion cards hosting memory alone, such as: 3D-stacked memory, high-bandwidth multi-channel RAM, unified/shared memory on accelerators, Compute Express Link (CXL)-based architectures, persistent memory, or MRDIMMs.

As in previous years, the Workshop on Heterogeneous Memory Systems, now rebranded as Heterogeneity and Memory Systems (HMEM), will bring together different research efforts and expertise to the end of integrating different approaches and democratizing the use of resource heterogeneity from a memory perspective, to benefit applications not only in terms of performance, but also energy efficiency and cost trade-offs. The main goal of the workshop is to push the research frontiers forward by exchanging knowledge and debating ideas through featured talks, technical paper presentations, and interactive discussions. Overall, topics of interest include, but are not limited to:

* Resource heterogeneity (e.g., accelerators) and memory implications,
including memory designs, data layouts, etc.
* Data allocation and placement techniques in heterogeneous memory systems
* Caching for heterogeneous memory systems
* Programming models and tools for complex/heterogeneous memory
hierarchies
* Software-defined far memories
* Disaggregated memory and in-memory computing
* Data movement in heterogeneous memory systems
* Memory consistency and persistency models
* Data structures for heterogeneous memory infrastructures
* Abstractions and support for failure-atomicity in persistent memory
* Emerging memory architectures and system configurations
* AI on heterogeneous memory systems and use of AI for heterogeneous
memory systems
* Use cases, early experiences and performance evaluations

Submissions
====================

This is a traditional-style workshop without formal proceedings. The authors of accepted submissions will give a talk at the workshop and participate in the closing discussion panel. Additionally, authors will be invited to (optionally) upload their submitted paper (PDF) to be shared on the workshop website. A paper accepted to the HMEM workshop does not preclude its future publication at a major conference.

Submissions must use the IEEE proceedings template (https://www.ieee.org/conferences/publishing/templates), two-column page format (U.S. letter – 8.5″ x 11″).

We accept two types of submissions.

A first type of submission includes position papers as well as papers that describe completed or early-stage work. Such submissions are limited to 10 pages including references and figures, but excluding bibliography.

We also welcome 2-page abstracts that summarize recently accepted/published at top-tier conferences/journals.

Submit your paper here: https://submissions.supercomputing.org


Important dates
====================

* *Submission deadline: August 17, 2026*
* Notification of acceptance: September 15, 2026

Time Zone: AOE (Anywhere One Earth)


Organization committee
====================
Harald Servat, Intel
João Barreto, INESC-ID, Universidade de Lisboa
Antonio J. Peña, Barcelona Supercomputing Center (BSC)


Program commitee
====================

* Alexandro Baldassin, UNESP, Brazil
* Brice Videau, Argonne National Laboratory, USA
* Chloe Alverti, National Technical University of Athens, Greece
* Clément Foyer, Université de Reims Champagne-Ardenne, France
* Gulay Yalçin, Ankara Yildirim Beyazit University, Turkey
* Maciej Maciejewski, Huwaei, Poland
* Manolis Marazakis, Foundation for Research and Technology – Hellas
(FORTH), Greece
* Marc Jorda, Barcelona Supercomputing Center (BSC), Spain
* Petar Radojkovic, Barcelona Supercomputing Center (BSC); Polytechnic
University of Catalonia, Spain
* Sudharshan S. Vazhkudai, Micron Technology Inc, USA
* Tim Dykes, Hewlett Packard Enterprise (HPE), UK