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The International Symposium on Memory Systems - Inaugural meeting, October 2015, Washington DC
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Call for Papers - www.memsys.io

Important Dates

Submission: April 6*, 2015
Notification: June 15, 2015
Camera-Ready: July 31, 2015

* There will be an automatic submission extension of one week

Paper Formats

2 page Extended Abstracts
5–6 page Position Papers
10–12 page Research Papers

Conference paper layout, no less than 9pt font in body, two-column, blind submission, up to 12 pages in length.
All accepted submissions will be presented and included in the printed conference proceedings.
Note: Submitting either Extended Abstracts or Position Papers will not preclude an author from submitting their work, in a longer research format, to another publication forum at a later date.

Overview

The memory system has become extremely important recently: memory is slow, and this is the primary reason that computers don’t run significantly faster than they do. In large-scale computer installations such as the building-sized systems powering Google.com, Amazon.com, and the financial sector, memory is often the largest dollar cost as well as the largest consumer of energy. Consequently, improvements in the memory system can have significant impact on the real world, improving power and energy, performance, and/or dollar cost.
Moreover, many of the problems we see in the memory system are cross-disciplinary in nature—their solution would likely require work at all levels, from applications to circuits. Thus, while the scope of the problem is memory, the scope of the solutions will be much wider.

Areas of Interest

Previously unpublished papers containing significant novel ideas and technical results are solicited. Papers that focus on architecture level concepts, outside of traditional conference scopes, will be preferred over others (e.g., the desired focus is away from pipeline design, processor cache design, prefetching, data prediction, etc.). Symposium topics include, but are not limited to, the following areas:

• Memory system design
• Memory controller design
• Operating system design for hybrid memories
• Memory technology, including flash, DRAM, PCM, STT-RAM, etc.
• Data-movement issues and mitigation techniques
• Interconnects to support large-scale data movement
• Software techniques for distributed memories
• Memory-focused power & energy optimizations
• Novel system architectures
• Near-memory computing
• Memory-centric programming models
• Memory failure modes
• Memory and system security

To reiterate, papers that focus on topics outside of traditional conference scopes will be preferred over others.

Submission Formats

In the conference’s first year, we will accept extended abstracts, position papers, and/or research papers. The only limitation is the typical architecture conference twelve-page format. Our primary goal is to showcase interesting ideas that will spark conversation between disparate groups—to get applications people and operating systems people and system architecture people and interconnect people and circuits people to talk to each other.

Conference Organizers

Bruce Jacob, U. Maryland
Ameen Akel, Micron
James Ang, Sandia
Ishwar Bhati, Oracle
Angelos Bilas, FORTH
Mu-Tien Chang, Samsung
Zeshan Chishti, Intel
Skevos Evripidou, U. Cyprus
Brinda Ganesh, Intel
Georgi Gaydadjiev, Maxeler
James Goodman, Auckland/Wisconsin
Hillery Hunter, IBM
Bharath Iyer, Samsung
Aamer Jaleel, NVIDIA
David Kaeli, Northeastern
Dean Klein, Micron
Hsien-Hsin Lee, TSMC
Gabriel Loh, AMD
Shih-Lien Lu, Intel
Sally McKee, Chalmers
Avi Mendelson, Technion
Trevor Mudge, U. Michigan
Richard Murphy, Micron
David Resnick, Sandia
Scott Rixner, Rice
Arun Rodrigues, Sandia
Kevin Skadron, U. Virginia
Sadagopan Srinivasan, AMD
Pedro Trancoso, U. Cyprus
Ankush Varma, Intel
Robert Voigt, Northrop Grumman
David Wang, Inphi