SCOPE AND OBJECTIVES
Computational, storage, accelerators, and sensing resources are required to be interconnected in efficient ways in most complex systems such as data-centre and cloud infrastructures, data centers, cyber –physical –security systems, many-core processors, and reconfigurable platforms.
This workshop is concerned with the design of high performance interconnection networks for such complex systems. Also of interest is to explore systems using HPIN.

The goal of this workshop is to bring together the researchers from academia and the experts from industry to present and discuss innovative ideas and solutions in high performance interconnection networks.

Selected high-quality papers from the workshop will be invited for extension and publication in special issues in the International Journal of Embedded and Real-Time Communication Systems (IJERTCS) or the Springer’s computing journal.

The workshop topics include (but are not limited to) the following:

- Multi-core on-chip Interconnects, Clusters interconnects, Systems interconnects, and Data centers Interconnects
- Hardware and software architectures and implementations for interconnection networks
- On/Off-chip interconnection network architecture (topology, routing, arbitration, ...)
- (Self-aware) Quality of Service
- Design, implementation, and evaluation of interconnect standards (InfiniBand, Ethernet, PCI-Express, HyperTransport)
- Performance and power management issues
- System modelling and simulation
- Reliability, scalability, availability, and fault tolerance
- (Self-aware) reconfigurability issues
- Memory system design and optimizations
- Implementing HPIN with FPGAs
- HPIN in cyber physical systems
- HPIN in cyber security
- Application specific HPIN
- HPIN for data centers

Organizers:
Masoumeh Ebrahimi, University of Turku, Finland
Masoud Daneshtalab, University of Turku, Finland
Jouni Isoaho, University of Turku, Finland