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TECS 2013 : Special Issue on Design Challenges for Many-core Processors - ACM Transactions on Embedded Computing Systems (TECS) | |||||||||||||||
Link: http://acmtecs.acm.org/si/12/dcmp12.htm | |||||||||||||||
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Call For Papers | |||||||||||||||
General Scope
Many-core processors are moving towards the integration of hundreds cores on a single chip and hold the promise of increasing performance through parallelism. As the number of cores integrated into a chip increases, the on-chip communication becomes power and performance bottleneck in future many-core processors. Network-on-Chip (NoC) architecture has been proposed as the most viable solution to meet the performance and design productivity requirements of the complex on-chip communication infrastructure. NoC provides an infrastructure for better modularity, scalability, fault-tolerance, and higher bandwidth compared to traditional infrastructures. On the other hand, developing applications using the full power of NoC-based many-core processors requires software developers to transition from writing serial programs to writing parallel programs. On top of that, for managing many-core resources, contemporary Operating Systems (OS) have been designed to run on a small number of reliable cores and are not able to scale up to hundreds of cores. Therefore, designing scalable and faultless OSs will be a tremendous challenge in future many-core processors. The goal of this special issue is to present and discuss innovative ideas and solutions in the design, modeling, prototyping, programming, and implementation of many-core processors. Topics of interest include but are not limited to: • NoCs (routing, arbitration, switch architecture, etc.) • Mapping of applications (static, dynamic, etc.) • OS (centralized, distributed, scheduling, allocation, memory management, etc.) • Reliability issues • Physical design • 3D stacked technology • Synthesis, verification, debug & test • Performance and power issues • Reconfigurability aspects • FPGA implementation • Programming model and scalable software • Compiler technologies • Many-core as accelerators • Many-core embedded systems • Heterogeneity challenges Submitted articles must not have been previously published or currently submitted for publication elsewhere. For work that has been published previously in a workshop or conference, it is required that submissions to the special issue have at least 40% new content. Submissions that do not meet this requirement will be rejected without review. Guest Editors, Masoud Daneshtalab, University of Turku, Finland (masoud.daneshtalab@utu.fi) Maurizio Palesi, University of Enna, “Kore”, Italy (maurizio.palesi@unikore.it) Juha Plosila, University of Turku, Finland (juha.plosila@utu.fi) |
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