IEEE Micro Special Issue on Heterogeneous Computing

Call for Papers


Guest Co-Editors:
Dean Tullsen (UCSD)
Ravishankar Iyer (Intel)

Submissions due: Jan 16, 2015
Publication date: July-August 2015

Heterogeneity is widely accepted as a fruitful avenue to improve performance and power/energy/thermal-efficiency in the face of continued technology miniaturization (Moore’s Law) and slowed supply voltage reduction (end of Dennard scaling). Heterogeneity comes in many flavors ranging from Systems-on-Chip (SoCs) with specialized hardware accelerators, to hybrid CPU/GPU architectures, to single-ISA heterogeneous multi-cores with different core types, to multi-ISA heterogeneous multi-cores in which different core types implement different Instruction-Set Architectures (ISA). Architects have explored and built heterogeneous architectures across a broad spectrum of computing devices including embedded systems, mobile devices, datacenters, and High-Performance Computing (HPC) supercomputers. While the performance and power/energy opportunities have been outlined, important challenges are yet to be studied regarding architecture, accelerators, hardware/software interface, run-time support, compilation, programming models, and performance evaluation. The goal of this Special Issue is to present the latest state-of-the-art results in the broad area of heterogeneous computing systems.

Areas of interest include, but are not limited to:

- Heterogeneous architectures, including:
o System-on-Chip (SoC) with accelerators
o CPU/GPU systems
o Single-ISA heterogeneous multi-cores
o Multi-ISA heterogeneous multi-cores
- Roadmaps and commercial trends in heterogeneous architectures
- Trade-offs in performance, power, energy, thermal, reliability, code portability and programmability due to heterogeneity
- Case studies of heterogeneous architectures in embedded system design, mobile computing, HPC, data centers, etc.
- Accelerator architectures and interfaces
- Platform support for heterogeneous and accelerator architectures
- Hardware/software interactions on heterogeneous architectures, including OS scheduling and compilation
- Programming models and runtime support for heterogeneous architectures
- Workloads particularly suited for heterogeneity
- Performance evaluation of heterogeneous architectures
- Experiences with real heterogeneous platforms

Submission procedure:
Log onto IEEE CS Manuscript Central ( https://mc.manuscriptcentral.com/micro-cs) and submit your manuscript. Please direct questions to the IEEE Micro magazine assistant (micro­ma@computer.org) regarding the submission site. For the manuscript submission, acceptable file formats include Microsoft Word and PDF. Manuscripts should not exceed 5,000 words including references, with each average­size figure counting as 150 words toward this limit. Please include all figures and tables, as well as a cover page with author contact information (name, postal address, phone, fax, and e­mail address) and a 200­word abstract. Submitted manuscripts must not have been previously published or currently submitted for publication elsewhere, and all manuscripts must be cleared for publication. All previously published papers must have at least 30% new content compared to any conference (or other) publication. Accepted articles will be edited for structure, style, clarity, and readability. For more information, please visit the IEEE Micro Author Center (http://www2.computer.org/portal/web/peerreviewmagazines/acmicro).

Important dates:
Initial submissions due: Jan 16, 2015
Author notification: March 2, 2015
Revised papers due: March 20, 2015
Final version due: April 23, 2015
Publication timeframe: July-August 2015

Questions?
Contact the Guest Co-Editors Dean Tullsen (tullsen@ucsd.edu) and Ravi Iyer (ravishankar.iyer@intel.com), or the Editor-in-Chief Lieven Eeckhout (lieven.eeckhout@ugent.be).