The goal of FastPath is to bring together researchers and practitioners involved in cross-stack hardware/software performance analysis, modeling, and evaluation of workload optimized systems. With microprocessor clock speeds being held constant, optimizing systems around specific workloads is an increasingly attractive means to improve performance. More precisely, workload optimized systems have hardware and/or software specifically designed to run well for a particular application or application class. The types and components of workload optimized systems vary, but a partial list includes traditional CPUs assisted with accelerators (ASICs, FPGAs, GPUs), memory accelerators, I/O accelerators, hybrid systems, converged infrastructure, and IT appliances. The importance of workload optimized systems is seen in their ubiquitous deployment in diverse systems from cellphones to tablets to routers to game machines to Top500 supercomputers. Prominent commercial examples of workload optimized systems include IBM DataPower, IBM Purescale Application System, IBM Watson, Oracle Exadata, and HP Moonshot Servers. Exploiting CPU savings and speed-ups offered by workload optimized systems for application level performance improvement poses several cross stack hardware and software challenges. These include developing alternate programming models to exploit massive parallelism offered by accelerators, designing low-latency, high-throughput H/W-S/W interfaces, developing techniques to efficiently map processing logic on hardware, and cross system stack performance optimization and tuning. Emerging infrastructure supporting big data analytics, cognitive computing, large-scale machine learning, mobile computing, and internet-of-things, further exemplify workload optimized design at large.

Topics

FastPath seeks to facilitate the exchange of ideas on performance analysis and evaluation of workload optimized systems and seeks papers on a wide range of topics including, but not limited to:


Workload characterization and profiling
Industrial experiences
GPUs, FPGAs, ASIC accelerators
Memory, I/O, Storage, Network accelerators
Hardware/Software co-design
Workload optimized servers
Hybrid/Heterogeneous systems
Measurements and Experimentation
Analytical techniques
Performance modeling and prediction
Performance tooling and optimization
Programming models for workload optimized systems
Runtime management systems
Workload scheduling and orchestration
Workload optimized clusters in Cloud
Systems for Big-Data Analytics
Systems for Large-scale machine learning
Intelligent/Cognitive systems
Mobile computing systems
Converged/integrated infrastructure
Workload optimized systems from specific domains, e.g., financial, biological, education, commerce, healthcare.

Submission

Following the detailed instructions on the FastPath website, authors should submit PDF of a 2-4 page extended abstract by the submission deadline. The submission should follow standard format (2-column, 10 to 12-point type, single spaced, 1-inch margins). Abstracts should provide sufficient detail about the work and its technical contributions.

Authors of selected abstracts will be invited to present their work at the workshop. Accepted abstracts will be made available through the workshop website and hard copies will be provided at the workshop to the attendees. There are no copyright issues with FastPath, and thus authors retain the copyright of their work with complete freedom to submit their work elsewhere.

Key Dates

Submission: March 1, 2015
Notification: March 10, 2015
Final Materials / Workshop: March 29, 2015

Organizers

General Chair: Erik Altman (IBM)
Program Committee Chairs: Vijay Janapa Reddi (U-Texas, Austin),
Parijat Dube (IBM)
Web Chair: Augusto Vega (IBM)

Program Committee

David Brooks Harvard University
Trey Cain Qualcomm Research
Mike Ferdman Stony Brook University
Sudhanva Gurumurthi AMD, University of Virginia
Eric Van Hensbergen ARM Research
Arrvindh Shriraman Simon Fraser University
Devesh Tiwari Oak Ridge National Lab
Sudhakar Yalamanchili Georgia Tech
Chuanjun Zhang Intel