DAC 2027 Research Manuscript CFP

DAC 2027, “The Chips to Systems Conference,” invites original research manuscripts on design and design automation of electronic circuits and systems. The major areas are AI, Design, EDA, Security, and Systems, with particular cross-cutting interest in Low Power, Chiplets, 3D-IC, and Quantum Computing. Recent acceptance rates have been approximately 20–25%.

📅 Important dates
Milestone DeadlineAbstract submission Nov. 11, 2026, 5:00 PM US Pacific
Full manuscript submission Nov. 18, 2026, 5:00 PM US Pacific
Accepted paper IDs published Feb. 22, 2027
Acceptance/rejection notification Mar. 8, 2027
Manuscript confirmation Mar. 22, 2027
Proceedings manuscript Mar. 31, 2027
Author registration Apr. 10, 2027
Draft slides Apr. 15, 2027
Final slides May 21, 2027
DAC begins Jul. 11, 2027
Submission requirements
Stage 1, Abstract: title, approximately 100-word abstract, and all co-authors must be entered by Nov. 11. Names, affiliations, countries, email addresses, and conflicts of interest with TPC members are required. The manuscript may optionally be uploaded at this stage.
Stage 2, Manuscript: maximum 6 pages + 1 additional references-only page, due Nov. 18.
Work must be original, not previously published in indexed research databases, and not simultaneously under review at another conference or journal.
Authors should treat the submission as finished. There is no post-deadline opportunity to fix submission-rule problems.
Review is double-blind. Related unpublished/under-review work that could compromise anonymity is handled through DAC's separate disclosure process.
Publication in IEEE Xplore and the ACM Digital Library is conditional on conference registration and presentation at the poster session.
AI-related CFP topics

This year's CFP is particularly relevant to agentic AI / AI-for-hardware work. The AI1: AI/ML Frontiers for Hardware Design category explicitly solicits:

AI1.1 Benchmarks, datasets, and model evaluation for EDA
AI1.2 Agentic AI for synthesis, physical design, and circuit design
AI1.3 Agentic AI for RTL generation and PPA-driven refinement
AI1.4 Agentic AI for verification
AI1.5 AI-based chip design flow automation
AI1.6 Foundation models for EDA
AI1.7 AI/ML for hardware architecture design-space exploration

Other AI categories cover AI/ML algorithms and models (AI2), applications and systems (AI3), architecture design (AI4), and infrastructure/platform design (AI5), including hardware/software co-design and specialized AI systems.

AI/LLM policy

Use of LLM-generated text, figures, images, or code is permitted, but such use generally must be disclosed in a dedicated**“Content Generated by AI”** section, identifying the LLM, affected sections, and how it was used. Routine editing, grammar improvement, translation, and knowledge retrieval generally do not require disclosure, although disclosure is recommended. LLMs cannot be authors, and authors remain responsible for all submitted content.

DAC 2027 also says it will pilot a controlled LLM system during review. It will generate an additional report only after human reviews have been submitted and locked; the system will not score papers, recommend acceptance, or make decisions. Final authority remains with human reviewers/TPC leadership.

For an agentic-AI-for-chip-design paper, AI1.2–AI1.5 are especially direct fits, depending on whether the core contribution is synthesis/physical design, RTL/PPA optimization, verification, or end-to-end design-flow automation.