Effective compilers allow more efficient execution of application programs on a given computer architecture. On the other hand, well-conceived architectural features can support more effective compiler optimization techniques. Good interaction between compilers and computer architectures is the key to successful design of highly efficient and effective computer systems. This workshop is to promote new ideas and present recent developments in compiler techniques and computer architectures that enhance each other¡¯s capabilities and performance. Papers are solicited on any aspect of interaction between compilers and architectures in the design of microprocessors, multiprocessors, and other parallel computer systems.

Potential topics, not limited to:
Processor reliability enhancement
Improved timing analysis and predictability
Secure, dependable computing
Managed and unmanaged run-time support
Dynamic compilation and optimization
Task synchronization and scheduling
System virtualization
Efficient I/O support
Parallelism enhancement and exploitation
Memory, cache, and register management
Multi-core software and compilation
Code optimization and generation
Low power architecture and software
Debugging, verification and validation
Processor variation interactions with software
Network on chips