SCOPE
The Euromicro Conference on Digital System Design (DSD) addresses all aspects of digital system design from embedded and mixed hardware/software system engineering, down to microarchitectures, digital circuits and VLSI techniques. It focuses on advanced circuit and system design and design automation concepts, paradigms, methods and tools, as well as on modern implementation technologies from full custom in nanometer technology nodes to FPGA and to multicore infrastructures. Compiler assisted ASIP, CMP, SMP, SMT, DSP-VLIW, GPU and platform based system design research results are welcome. Design and Verification Languages and Standards, Modeling, High Level Synthesis, Productive Design Technology and Engineering Flows, Efficiency, Density, Signal Integrity, Testability, Timing Analysis and Timing Closure, Power Consumption, Computational Power Speed and Performance, Manufacturability, Cost, Reliability, Error Resilience, Complexity, or Process Variability issues are covered in DSD.
Euromicro was founded in 1973 by Rodnay Zaks and other colleagues shortly after the announcement of the Intel 4004 landmark processor. IEEE Computer Society publishes the DSD Proceedings which are available worldwide through IEEE Xplore Digital Library.

MAIN TOPICS
T1: (SS) - System synthesis. High-level, behavioral, register-transfer, logic and physical circuit synthesis; arithmetic, signal processing and vector processing units; graphics processing units and hardware accelerators; memory design; communication architecture and protocols; specific circuits and processors; multi-objective optimization observing power, performance, communication traffic, interconnect architecture, layout, technology, reliability, robustness, security, testability and other issues; management of parallel computational resources, memory allocation and hierarchy; hardware/software co-design; mapping of applications and architectures; algorithm architecture matching; transaction level modeling and higher-level modeling; virtual system prototyping; design space exploration; synthesis of asynchronous and dataflow driven systems.
T2: (MPSoC) - Systems-on-a-chip and Multiprocessor SoCs. Generic system platforms and platform-based design; CMP, SMP, SMT, DSP and VLIW (multi)processor architecture and enhancements; networks on chip; power, energy, timing, predictability and other quality issues; IP design, standardization and reuse; virtual components; compiler assisted ASIP and MPSoC generation and configuration; hardware support for embedded kernels; embedded software features; SoC design environments for embedded systems, sequential and parallel applications; static, run-time and dynamic optimizations of embedded systems; performance metrics.
T3: (RC) - Programmable/re-configurable architectures. Processor, communication, memory and software architectures with focus on application specific and/or embedded computing; systems on re-configurable chip; system FPGAs and structured ASICs and co-processors; processing arrays; programmable fabrics; novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.); compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software; optimization of FPGA-based cores; novel design algorithms for FPGA features; embedded software; CAD for placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification; CAD for modeling, analysis and optimization of timing and power; high-level models and tools for FPGAs; rapid prototyping.
T4: (SMVT) - System, hardware and embedded-software specification, modeling, verification and test. Design and verification languages; functional, structural and parametric specification and modeling; simulation, emulation, prototyping, and testing at the system, register-transfer, logic and physical levels; co-simulation and co-verification.
T5: (APP) - Applications of (embedded) digital systems with emphasis on demanding and new applications in fields such as: (wireless) communication and networking; measurement and control; health-care and medicine; military, space, avionics and automotive systems; surveillance and security; networked and electronic media; multimedia design; real time signal processing hardware; digital video technology; consumer electronics; ambient intelligence; wireless sensor networks; ubiquitous, wearable and implanted systems.
T6: (ET) - Emerging technologies, system paradigms and design methodologies. Deep sub-micron VLSI design issues; digital design in 3D layouts; optical, bio, nano and quantum technologies and computing; self-organizing and self-adapting systems.

SUBMISSION GUIDELINES
Regular Papers:
Prospective authors are encouraged to submit their manuscripts for review electronically trough the following web page (http://www.conftool.net/dsd2009/) or by sending the paper to the Program Chair via email (antonio.nunez@iuma.ulpgc.es), only if an unexpected web access problem is encountered) before the deadline for submission.
Each manuscript should include the complete paper text, all illustrations, and references. The manuscript should conform to the required IEEE format: single-spaced, double column, A4/US letter page size, 10-point size Times Roman font, up to 8 pages. In order to conduct a blind review, no indication of the authors' names should appear in the submitted manuscript, references included.
Case Studies and Application Papers:
Submissions can be made which report on state-of-the-art digital systems, digital designs, architectures, design methods and/or tools, and (embedded) applications. Papers discussing lessons learned from practical experience, demanding or new applications, and experimental research are particularly encouraged. Manuscripts may be submitted in the same way as regular papers.
The Program Committee will decide if papers will be accepted for a long presentation (30 minutes), short presentation (15 minutes) or as a poster. For long and short presentations, 8 pages will be assigned in the published proceedings. A poster presentation will be assigned 4 pages. Papers exceeding the page limit will be charged 50 Euro per page in excess. If the paper is accepted, at least one of the authors must pre-register and pay the conference fee before the deadline for submitting the camera-ready paper. Otherwise the paper will not be published in the proceedings.