Call for Papers

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip and chip-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, embedded systems, and design automation. Topics of interest include, but are not limited to:

NoC Architecture and Implementation:
Network architecture (topology, routing, arbitration)
NoC Quality of Service
Timing, synchronous/asynchronous communication
NoC reliability issues
Network interface issues
NoC design methodologies and tools
Signaling & circuit design for NoC links
Physical design of interconnect & NoC

NoC Application:
Mapping of applications onto NoCs
NoC case studies, application-specific NoC design
NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
NoC designs for heterogeneous systems, fused CPU-GPU architectures, etc
Network design for 2.5D & 3D stacked logic and memory

NoC Analysis and Verification:
Power, energy & thermal issues (at the NoC, un-core and/or system-level)
Benchmarking & experience with real NoC-based hardware
Modeling, simulation, and synthesis of NoCs
Verification, debug & test of NoCs
Metrics and benchmarks for NoCs

NoC at the un-core and system-level:
Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols & NoCs
NoC support for memory and cache access
OS support for NoCs
Programming models including shared memory, message passing and novel programming models
Multi/many-core workload characterization & evaluation
Optical, RF, & emerging technologies for on-chip/inpackage interconnects Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

Submission Rules

Electronic paper submission requires a full paper, up to 8 double-column IEEE format pages, including figures and references. The program committee in a double-blind review process will evaluate papers based on scientific merit, innovation, relevance, and presentation. Submitted papers must describe original work that has not been published before or is under review by another conference at the same time. Each submission will be checked for any significant similarity to previously published works or for simultaneous submission to other archival venues, and such papers will be rejected. Furthermore, NOCS will notify the technical chair of the venue where the duplicate was submitted. Please see the paper submission instructions for details.

Proposals for tutorials, special sessions, panels are also invited. Please see the detailed submission instructions for paper, tutorial, special sessions, and panel proposals at the submission page. A special section related to the theme of the conference will be organized in one of the IEEE journals.


Important Dates

Abstract registration deadline Dec. 4, 2012
Full paper submission deadline Dec. 7, 2012
Proposals for tutorials, special sessions and panels Jan 11, 2013
Notification of acceptance Feb 1, 2013
Final version due Mar 1, 2013

Organizing Committee

General Co-Chairs:
Karam S. Chatha, Arizona State University, USA
Chita R. Das, Penn State University, USA
Finance Chair:
Sudeep Pasricha, Colorado State, USA
Registration Chair:
Mohammed Al Faruque, University of California-Riverside, USA
Publicity Chair:
Carole-Jean Wu, Arizona State University, USA
Program Co-Chairs:
John Bainbridge, Sonics Inc., USA
Natalie Enright Jerger, University of Toronto, CA
Publications Chair:
Paul Gratz, Texas A&M, USA
Tutorials/Demo Chair
Zhonghai Lu, KTH, Sweden
Industrial Chair
Umit Ogras, Intel, USA

Contact Information
Karam Chatha, kchatha@asu.edu
John Bainbridge, jbainbridge@ieee.org
Chita Das, das@cse.psu.edu
Natalie Enright Jerger, enright@eecg.toronto.edu