The annual CHES conference highlights new results in the design and analysis of cryptographic hardware and software implementations. The conference builds a valuable bridge between the research and cryptographic engineering communities and attracts participants from industry, academia, and government organizations. In addition to a single track of high-quality presentations, CHES 2016 will offer invited talks, tutorials, a poster session, a rump session, and a panel discussion. All submitted papers will be reviewed by at least four Program Committee members and authors will be invited to submit brief rebuttals of the reviews before the final decisions are made. Topics suitable for CHES 2016 include, but are not limited to:

Cryptographic implementations

Hardware architectures
Cryptographic processors and co-processors
True and pseudorandom number generators
Physical unclonable functions (PUFs)
Efficient software implementations

Attacks against implementations and countermeasures

Side channel attacks and countermeasures
Fault attacks and countermeasures
Hardware tampering and tamper-resistance
White-box cryptography and code obfuscation
Hardware and software reverse engineering

Tools and methodologies

Computer aided cryptographic engineering
Verification methods and tools for secure design
Metrics for the security of embedded systems
Secure programming techniques
FPGA design security
Formal methods for secure hardware

Interactions between cryptographic theory and implementation issues

New and emerging cryptographic algorithms and protocols targeting embedded devices
Special-purpose hardware for cryptanalysis
Leakage resilient cryptography

Applications

Cryptography and security for the Internet of Things (RFID, sensor networks, smart devices, smart meters, etc.)
Hardware IP protection and anti-counterfeiting
Reconfigurable hardware for cryptography
Smart card processors, systems and applications
Security for cyberphysical systems (home automation, medical implants, industrial control, etc.)
Automotive security
Secure storage devices (memories, disks, etc.)
Technologies and hardware for content protection
Trusted computing platforms

Instructions for CHES Authors

Authors are invited to submit original papers via electronic submission. Details of the electronic submission procedure will be posted on the CHES webpage when the system is activated. Submissions must be anonymous, with no author names, affiliations, acknowledgements, or obvious references. Papers should begin with a title, a short abstract, and a list of keywords. All submissions must follow Springer's LNCS format with a total page limit of 18 pages excluding references. Supplementary materials that facilitate verification of the results, e.g. source code, proof details, etc., may be appended without a page limit or uploaded as separate files, but reviewers are neither required to read them nor will they be printed in the proceedings. Hence submissions must be intelligible and self-contained within the 18 pages bound. Papers should have page numbers to facilitate their review. In Latex this can be achieved for instance using \pagestyle{plain}.
All submissions will be blind-refereed and submissions which substantially duplicate work published elsewhere, or submitted in parallel to any other conference or workshop with proceedings, will be instantly rejected: see the IACR Policy on Irregular Submissions and the Guidelines for Authors. Note that any submission to CHES 2016 implies the full acknowledgement and commitment of the authors to the entire review process. A withdrawal of any paper prior to the notification deadline will be accepted only in exceptional cases (i.e., severe technical flaws discovered after the submission deadline).
Details of the electronic submission procedure will be posted on the conference website. The final proceedings of CHES 2016 will be published by Springer in the LNCS series and accepted papers must conform to Springer publishing requirements. At least one author of an accepted paper must attend CHES 2016 to present the paper.

Important Dates

Submission deadline: March 4, 2016, 23:59PST
Referee comments to authors: April 22nd, 2016
Author response to comments: April 28th, 2016
Acceptance notification: May 16th, 2016
Final version due: June 6th, 2016
Workshop presentations: August 17th - 19th, 2016

Mailing List

If you want to receive subsequent Call for Papers and registration information, please send a brief mail to mailinglist@chesworkshop.org. Your details will only be used for sending CHES related information.

Program Committee

J. Balasch, KU Leuven, BE
L. Batina, Radboud University Nijmegen, NL
D.J. Bernstein, University of Illinois at Chicago, USA and Technische Universiteit Eindhoven, NL
G. Bertoni, STMicroelectronics,IT
C.-M. Cheng, National Taiwan University, TW
E. De Mulder, Cryptography Research, US
H. Drexler, Giesecke & Devrient, DE
O. Dunkelman, University of Haifa, IL
J. Fan, Open Security Research, CN
S. Faust, Ruhr-Universität Bochum, DE
V. Fischer, Jean Monnet University Saint-Etienne, FR
W. Fischer, Infineon Technologies, DE
B. Gierlichs, KU Leuven, BE
C. Giraud, Oberthur Technologies, FR
D. Holcomb, University of Massachusetts Amherst, US
N. Homma, Tohoku University, JP
M. Hutter, Cryptography Research, US
K. Järvinen, Aalto University, FI
M. Joye, Technicolor, FR
L. R. Knudsen, Technical University of Denmark, DK
K. Lemke-Rust, Bonn-Rhein-Sieg University of Applied Sciences, DE
T. Lepoint, CryptoExperts, FR
Y. Li, Nanjing University of Aeronautics and Astronautics, CN
R. Maes, Intrinsic-ID, NL
M. Matsui, Mitsubishi Electric, JP
M. Medwed, NXP Semiconductors, AT
A. Moradi, Ruhr-Universität Bochum, DE
D. Mukhopadhyay, Indian Institute of Technology Kharagpur, IN
D. Naccache, Ecole Normale Superieure, FR
E. Oswald, University of Bristol, UK
D. Page, University of Bristol, UK
T. Peyrin, Nanyang Technological University, SG
A. Poschmann, Nanyang Technological University, SG
E. Prouff, ANSSI, FR
F. Regazzoni, ALaRI, Lugano, CH
M. Rivain, CryptoExperts, FR
A. Schlösser, NXP Semiconductors, DE
S. Skorobogatov, University of Cambridge, UK
M. Sönmez Turan, NIST, US.
M. Stöttinger, Continental Teves, DE.
B. Sunar, Worcester Polytechnic Institute, US
H. Thiebeauld, eshard, FR
O. Thomas, Texplained, FR
M. Tibouchi, NTT Secure Platform Laboratories, JP
S. Trimberger, Xilinx, US
I. Verbauwhede, KU Leuven, BE
A. Weimerskirch, University of Michigan, US
B. Wyseur, NAGRA, CH

Organizing Committee

All correspondence and/or questions regarding the technical program should be directed to the Program co-Chairs:

Benedikt Gierlichs
(Program co-Chair)
KU Leuven (Belgium)
Email: ches2016programchairs@iacr.org

Axel Poschmann
(Program co-Chair)
NXP Semiconductors (Germany)
Email: ches2016programchairs@iacr.org

Çetin Kaya Koç
(General Co-Chair)
University of California Santa Barbara (USA)
Email: koc@cs.ucsb.edu

Erkay Savaş
(General Co-Chair)
Sabanci University (Turkey)
Email: erkays@sabanciuniv.edu