=============================================================================
Call for Papers
(32nd Edition)
IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems
DFT 2019
ESA-ESTEC & TU Delft, Netherlands
October 2 – 4, 2019
http://www.dfts.org
=============================================================================

Dear colleague,
please find attached the Call For Papers of the IEEE International Symposium on
Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT 2019).

The symposium is going to Europe for its 32nd edition and will be co-hosted by
the Space Research and Technology Centre of the European Space Agency (ESA-ESTEC)
and TU Delft, Netherlands. The first two days of the symposium will be held at
ESA-ESTEC and the 3 rd day will be held at TU Delft. The city of Leiden - which is
between the two sites – is conveniently located close to Amsterdam International
Airport and is connected by excellent rail and bus services to both sites.

=== ABOUT DFT ===
DFT is an annual Symposium providing an open forum for presentations in the field
of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging
technologies. One of the unique features of this symposium is to combine new academic
research with state-of-the-art industrial data, necessary ingredients for significant
advances in this field. All aspects of design, manufacturing, test, reliability, and
availability that are affected by defects during manufacturing and by faults during
system operation are of interest.

=== IMPORTANT DATES ===
- Abstract submission: May 3, 2019
- Full paper submission: May 17, 2019
- Acceptance notification: July 12, 2019
- Camera ready deadline: August 9, 2019

=== PROGRAM TOPICS ===
The topics include (but are not limited to) the following ones:

1. YIELD ANALYSIS AND MODELING
Defect/fault analysis and models; statistical yield modeling; diagnosis; critical
area and other metrics.
2. TESTING TECHNIQUES
Built-in self-test; delay fault modeling and diagnosis; testing for analog and
mixed circuits; online testing; signal and clock integrity.
3. DESIGN FOR TESTABILITY IN IC DESIGN
FPGA, SoC, NoC, ASIC, low power design and microprocessors.
4. ERROR DETECTION, CORRECTION, AND RECOVERY
Self-testing and self-checking solutions; error-control coding; fault masking and
avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural
and system-level techniques.
5. DEPENDABILITY ANALYSIS AND VALIDATION
Fault injection techniques and frameworks; dependability and characterization.
6. REPAIR, RESTRUCTURING AND RECONFIGURATION
Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-
healing;
reliable FPGA-based systems.
7. DEFECT AND FAULT TOLERANCE
Reliable circuit/system synthesis; fault tolerant processes and design; design space
exploration for dependable systems, transient/soft faults.
8. RADIATION EFFECTS
SEEs on nanotechnologies; modeling of radiation environments; radiation experiments;
radiation hardening techniques.
9. AGING AND LIFETIME RELIABILITY
Aging characterization and modeling; design and run-time reliability, thermal,
and variability management and recovery.
10.DEPENDABLE APPLICATIONS AND CASE STUDIES
Methodologies and case studies for IoTs, automotive, railway, avionics and space,
autonomous systems, industrial control, etc.
11.EMERGING TECHNOLOGIES
Techniques for 2.5D/3D ICs, quantum computing architecttures, memristors, spintronics,
microfluidics, etc.
12.DESIGN FOR SECURITY
Fault attacks, fault tolerance-based countermeasures, scan-based attacks and countermeasures,
hardware trojans, security vs. reliability trade-offs, interaction between VLSI test, trust,
and reliability.

=== PAPER SUBMISSIONS ===
Prospective authors are invited to submit original and unpublished contributions.
Two types of submissions are possible: (i) regular papers (6 pages), and
(ii) short papers (4 pages). Both types will be included in the symposium
proceedings and should adhere to the IEEE conference template, 2-columns style
(available on conference web site), and submitted as PDF file, electronically.
Detailed information about the submission process will be available on the
symposium website.

Submissions are managed by means of EasyChair. Please register or use your existing login at
EasyChair to access the DFT 2019 area for submission at:

https://easychair.org/my/conference.cgi?conf=dfts2019

=== CALL FOR SPECIAL SESSIONS ===
DFT’19 seeks proposals for Special Sessions. The special sessions should aim at providing a
complementary experience with respect to the regular sessions by focusing on hot and emerging
topics of interest to the DFT community, as well as on multi-disciplinary topics, that are
expected to have a significant impact on DFT activities in the future (e.g. reliability aspects
in Approximate Computing, Quantum Computing, use of COTS Electronics for Space applications).
A special session could consist of a set of individual presentations or a panel, possibly with
experts from the industry.

Upon acceptance, special session presenters can prepare either a single paper for the entire
session or one paper per presenter to be included in the formal proceedings. For this reason,
papers (presenting original and unpublished contributions and that may be 4 pages or 6 pages long)
for special session will go through review process. For the single-session papers, it will be possible
to purchase 2 extra pages at an additional cost. Accepted papers will appear in the formal proceedings
of DFT 2019 symposium. Proceedings will be published by the IEEE Computer Society and will appear in
the Digital Library

Submitted proposals should include:

- a title of the special session
- a maximum 250-word abstract outlining the session's scope, topics and relevance for DFT symposium
- name, contact information and short biography of the organizer(s)
- format of the session: (1) panel or set of individual presentations, and (2) single paper per session
or one paper per presenter
- list of three/four contributed presentations (including titles, presenter names, contact information of
the corresponding presenter, and an abstract of each contribution). For panel proposals, list three to
five panelists and their area of expertise.

Proposal submissions should be presented in a single PDF to be sent via e-mail to the Special Session Chair:

Luigi Dilillo - dilillo@lirmm.fr

By means of their submission, all presenters agree to register for and participate to DFT’19, in case
their special session proposal is accepted.

- Special session submission: May 3, 2019
- Special session acceptance: May 17, 2019
- Special session papers submission: June 9, 2019
- Paper acceptance notification: July 9, 2019
- Camera ready: July 23, 2019

=== ORGANIZING COMMITTEE ===
- General co-chairs:
* Marco Ottavi (University of Rome "Tor Verata", IT - marco.ottavi@uniroma2.it)
* Antonios Tavoularis (European Space Agency, NL - antonios.tavoularis@esa.int)

- Program co-chairs:
* Vilas Sridharan (AMD, USA - vilas.sridharan@amd.com)
* Mihalis Psarakis (University of Piraeus, GR - mpsarak@unipi.gr)

- Special Session chair:
* Luigi Dilillo (LIRMM, FR - luigi.dilillo@lirmm.fr)

- Publicity/Web chair:
* Luca Cassano (Politecnico di Milano, IT)

- Publication chair:
* Prashant Nair (University of British Columbia)

- Local Arrangements co-chairs:
* Gianluca Furano (European Space Agency, NL)
* Alessandra Menicucci (TU Delft, NL)

================================================================================
We look forward to your contributions and your participation to the DFT 2019.

For updated information, please visit the DFT 2019 web site: http://www.dfts.org
================================================================================