The IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
provides a forum for exchanging ideas, discussing research results, and presenting practical applications in the areas of design, test, and diagnosis of nanoelectronic circuits and systems.
The symposium also offers an insight into relevant European R&D collaborative programs,
projects, and technology platforms.
The DDECS Symposium series has been organized by Central European countries: Czech
Republic (1997, 2002, 2006, 2009), Poland (1998, 2003, 2007), Slovakia (2000, 2004, 2008), Hungary (2001, 2005), Austria (2010) and Germany (2011).
DDECS 2012 will take place in Tallinn whose picturesque Old Town with its fascinating
medieval architecture and slender church spires is included in the UNESCO World Heritage
list. The Symposium is organized by Tallinn University of Technology and it is sponsored by the Test Technology Technical Council (TTTC) of the IEEE Computer Society.
Topics of interest include but are not limited to:
• ASIC/FPGA Design
• SoC and NoC Design and Test
• Bio-Inspired Hardware
• Design Verification/Validation
• Formal Methods in System Design
• Hardware/Software Co-Design
• IP-based Design
• Logic Synthesis
• Physical Design
• Defect/Fault Tolerance and Reliability
• Analog, Mixed-Signal, RF Design and Test
• Built-in Self-Test and Self-Repair
• Design for Testability and Diagnosis
• On-line Testing
• Embedded Systems Testing
• Memory, Processor Testing
• MEMS Testing
• Design and Test in Nano-Technologies
• ATE Hardware and Software
• Dependable HW/SW Systems

Submissions: Prospective authors are cordially invited to submit original papers using the electronic submission at the Symposium web page. Papers in English with a length of 6 pages maximum in IEEE conference style are expected. Dedicated student and industrial sessions, as well as embedded tutorials, will be organized at the symposium. Accepted papers will be included to the Symposium Proceedings and available through the IEEE Xplore Digital Library. The best papers from the symposium will be invited for submission to IEEE Design & Test of Computers. These papers will undergo the standard (but expedited) review process of D&T.

Key Dates
• Submission deadline: January 15th, 2012
• Notification of acceptance: March 3rd, 2012
• Camera ready: March 17th, 2012