DVCon is the premier conference on the application of languages, tools and
methodologies for the design and verification of electronic systems and
integrated circuits.The focus of the conference is on the usage of specialized
design and verification languages such as Verilog,SystemVerilog,VHDL,PSL
Syste mC, e, and V E RA, as well as general purpose languages such as C and C++.
Tools and methodologies include the use of te s t bench automation, hardwareassisted
verification, hardware/ software co- verification,assertion-based and
formal verification,and transaction- level system design and verification.
Conference attendees are primarily designers of electronic systems,ASICs and
FPGAs,as well as those involved in the research, development, and application
of Electronic Design Automation (EDA) tools. Presentations are highly technical
in nature,and reflect real life experiences in using these languages and too l s.
TOPIC SUGGESTIONS
We encourage you to contribute your experiences with hardware design and
verification languages, advanced tools and methodologies,and to participate in
the valuable exchange of ideas.
- Experience using ESL and/or TLM for system- level design and verification
- Experiences deploying a veri f i cation methodology libra ry
- Experiences with System- on- Chip design
- Designing and/or verifying complex ASICs and FPGAs
- Using multiple HDLs and/or HVLs in a design cycle
- Techniques for generating constrained- random test,or other automated
stimulus generation method s
- Synthesizing transaction- level or abstract designs from high-level languages such
as SystemC,System Verilog or C++,to RTL
- Experiences with hardware/ software co-design and co- verification
- Experiences with mixed-signal simulation
- Verification techniques that really work (and what did not work)
- Verification process and resource management
- Verification methods that have achieved zero functional bugs in
first silicon
- Assertion-based verification
- Coverage- driven verification
- Design and verification IP experiences, good and bad
- Measuring completeness and quality of verification: functional coverage,
code coverage or other techniques
- Experience with formal technologies applied to verification, including the
application of model checking and simulation together,or the use of
dynamic formal verification tools
- Any topic involving the use of an HDL or HVL