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CODES+ISSS 2018
Call for Papers
International Conference on
Hardware/Software Codesign and System Synthesis
September 30 – October 5, 2018, Torino, Italy
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The International Conference on Hardware/Software Codesign and System
Synthesis is the premier event in system-level design, modeling,
analysis, and implementation of modern embedded and cyber-physical
systems, from system-level specification and optimization down to system
synthesis of multi-processor hardware/software implementations. The
conference is a forum bringing together academic research and industrial
practice for all aspects related to system-level and hardware/software
co-design. High-quality original papers will be accepted for oral
presentation followed by interactive poster sessions. A special IoT Day
will be jointly organized by the conferences in ESWEEK. Articles aligned
to the topics of interest for CODES+ISSS, with distinct focus on IoT
platforms, wearables and other small form-factor devices are most welcome.


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Timeline
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Journal Track:
- Abstract Submission: March 27, 2018
- Full Paper Submission: April 3, 2018 (firm)
- Notification of Acceptance: July 1, 2018

Work-in-Progress Track:
- Paper Submission: May 30, 2018 (firm)
- Notification of Acceptance: July 1, 2018

Workshop Proposals: March 27, 2018
Tutorial Proposals: April 3, 2018


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Topics of Interests / Tracks
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Track 1) System-level design
Specification, modelling, refinement, system synthesis, partitioning,
hardware- software co-design, design space exploration, hybrid system
modelling and design, model-based design, and design for adaptivity and
reconfigurability.

Track 2) Domain and application-specific design
Analysis, design, and optimization techniques for multimedia, medical,
automotive, cyber-physical, and other specialized application domains.

Track 3) Embedded software
Language and library support, compilers, runtimes, parallelization,
software verification, memory and resource management, virtual machines,
operating systems, real-time support, and middleware.

Track 4) Safety, security and reliability
Cross-layer reliability, resilience and fault tolerance, test
methodology, design for testability, hardware and software security,
security for embedded and IoT devices, and cyber-physical system security.

Track 5) Simulation, validation and verification
Hardware/software co-simulation, verification and validation
methodologies, formal verification, hardware-accelerated simulation,
simulation and verification languages, models and benchmarks.

Track 6) System architecture
Heterogeneous systems, many-cores, networked and distributed systems.
architecture and micro-architecture design, exploration and optimization
including application-specific processors, reconfigurable architectures,
storage, memory and communication systems, and networks-on-chip.

Track 7) Power-aware systems
Power- and energy aware system design and methodologies ranging from
low-power embedded and cyber-physical systems to energy-efficient
large-scale systems such as cloud datacenters, green IT and smart grid.

Track 8) Industrial practices and case studies
Practical impact on current and/or future industries, application of
state-of-the-art methodologies and tools in various application areas
including wireless, networking, multimedia, automotive, cyber-physical,
medical systems, etc.


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Paper Process
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Journal-integrated Publication Model: ESWEEK 2018 will introduce a
journal-integrated publication model where the majority of papers will be
published in the IEEE Transactions on Computer Aided Design (TCAD).


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Organization
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CODES+ISSS Program Chairs:
Aviral Shrivastava, Arizona State University, US
Sudeep Pasricha, Colorado State University, US

ESWEEK General Chairs:
Soonhoi Ha, Seoul National University, KR
Petru Eles, Linköping University, SE

www.esweek.org