Important Dates

* Deadline for Paper Submission: July 10, 2007
* Notification of Acceptance: September 28, 2007
* Deadline for Final Version: November 16, 2007

Sponsored by

* IEEE Circuits and Systems Society (IEEE CASS)
* Association for Computing Machinery (ACM)'s Special Interest Group on Design Automation (SIGDA)
* The Institute of Electronics Engineers of Korea (IEEK)

Academically Sponsored by

* The Korea Information Science Society (KISS)

Areas of Interest

Original papers on, but not limited to, the following areas are invited.
[1] System Level Design:
System VLSI and SOC design methods, System specification, Specification languages, Design languages, Hardware-software co-design, Co-simulation, Co-verification, Platform-based design, Design reuse and IP�??s
[2] Embedded and Real-Time Systems:
Low power system design, Network on chip, Communication architecture, Memory architecture, Real-time OS and middleware, Compilation techniques, ASIP synthesis
[3] Behavioral/Logic Synthesis and Optimization:
Behavioral/RTL synthesis, Technology-independent optimization, Technology mapping, Interaction between logic design and layout, Sequential and asynchronous logic synthesis
[4] Validation and Verification for Behavioral/Logic Design:
Logic simulation, Symbolic simulation, Formal verification, Equivalence checking, Transaction-level/RTL and gate-level modeling and validation
[5] Physical Design (Routing):
Routing, Repeater issues, Interconnect optimization, Interconnect planning, Module generation, Layout verification
[6] Physical Design (Placement):
Placement, Floorplanning, Partitioning, Hierarchical design
[7] Timing, Power, Signal/Power Integrity Analysis and Optimization:
Timing analysis, Power analysis, Signal/power integrity, Clock and global signal design
[8] Interconnect, Device and Circuit Modeling and Simulation:
Interconnect modeling, Interconnect extraction, Package modeling, Circuit simulation, Device modeling/simulation, Library design, Design fabrics, Design for manufacturability, Yield optimization, Reliability analysis, Emerging technologies
[9] Test and Design for Testability:
Test design, Fault modeling, ATPG, BIST and DFT, Memory, core and system test
[10] Analog, RF and Mixed Signal Design and CAD:
Analog/RF synthesis, Analog layout, Verification, Simulation techniques, Noise analysis, Analog circuit testing, Mixed-signal design considerations
[11] Leading Edge Design Methodologies:
Novel design methodologies for SOCs, SIPs, IP-cores, processors, memories, A/D mixed circuits, Sensors, MEMS chips, FPGAs, reconfigurable systems, etc. and design examples based on the aforementioned methodologies